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參數資料
| 型號： | LF48410JC30 |
| 廠商： | LOGIC DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 1024 x 24-bit Video Histogrammer |
| 中文描述： | 24-BIT, DSP-HISTOGRAM PROCESSOR, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數： | 5/15頁 |
| 文件大?。?/td> | 302K |
| 代理商： | LF48410JC30 |
DEVICES INCORPORATED
Video Imaging Products
5
LF48410
1024 x 24-bit Video Histogrammer
08/08/2000–LDS.48410-L
example, to set the number of delays
to 10, START would have to be set
LOW every 6 cycles. The maximum
delay length is 1029 and the minimum
delay length is 6. Data on DIN
23-0
is latched on the rising edge of
CLK and loaded into the memory
array at the address defined by the
counter. Data is output on DIO
23-0
(if
RD is LOW). If the counter reaches
the value of 1023, the counter will
hold this value and writing to the
memory array will be disabled.
DELAY AND SUBTRACT MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 6.
The internal counter is used to gener-
ate address data for the memory
array. When START goes LOW, the
counter is reset to zero. Delay length
(row length) is determined by
reseting the counter every N–4 clock
cycles, where N is the number of
delays. The maximum delay length is
1029 and the minimum delay length
is 6. Data on DIN
23-0
is latched on the
rising edge of CLK and loaded into
the memory array at the address
defined by the counter. Data is
output on DIO
23-0
(if RD is LOW).
Before data read from the memory
array is output to DIO
23-0
, input data
is subtracted from it according to the
following formula: OUT
C
= D
(C–N+1)
–
D
(C–3)
. OUT
C
is the data sent to the
output port (DIO
23-0
) on clock cycle C.
D
(C–N+1)
is the data latched into the
device on clock cycle C–N+1, and D
(C-
3)
is the data latched into the device on
clock cycle C–3. N is the number of
delays. For example, to determine
what will be output on DIO
23-0
on
clock cycle 12 when the device is set
for 10 delays, set C=12 and N=10 to
obtain: OUT
12
= D
3
– D
9
. If the
counter reaches the value of 1023, the
counter will hold this value and
writing to the memory array will be
disabled.
ASYNCHRONOUS 16 MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure 7.
This mode allows the device to
function as an asynchronous single
port RAM. Each 24-bit memory
location is split into two parts, the
lower 16 bits and the upper 8 bits.
IOA
9-0
addresses the 24-bit memory
locations, and UWS addresses the
lower 16 or upper 8 bits of those
locations. If UWS is LOW, the lower
16 bits of the 24-bit memory location
are addressed. If UWS is HIGH, the
upper 8 bits are addressed. Address
data on IOA
9-0
and UWS is latched
into the device on the falling edge of
RD or WR. If RD latches the address
data, a memory read is performed.
Data at the specified address is
output on DIO
15-0
(if UWS was
latched LOW) or DIO
7-0
(if UWS was
latched HIGH). If UWS was latched
LOW/HIGH, DIO
16-23
/DIO
8-23
will
output zeros during a memory read.
If WR latches the address data, a
memory write is performed. After
the falling edge of WR latches the
address, data on DIO
15-0
(if UWS was
latched LOW) or DIO
7-0
(if UWS was
latched HIGH) is written to the RAM
on the rising edge of WR.
F
IGURE
6.
D
ELAY
A
ND
S
UBTRACT
M
ODE
F
IGURE
5.
D
ELAY
M
EMORY
M
ODE
RAM ARRAY
DATA IN
DATA OUT
ADDRESS
CONTROL
START
I/F
DIO
23-0
24
RD
COUNTER
(TO ALLCLK
DIN
23-0
24
3
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
–DIN
23-0
WR
RAM ARRAY
DATA IN
DATA OUT
ADDRESS
CONTROL
START
"0"
I/F
DIO
23-0
24
RD
COUNTER
(TO ALLCLK
DIN
23-0
24
3
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
WR
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