參數(shù)資料
型號(hào): LF3320
廠商: Logic Devices Incorporated
英文描述: Horizontal Digital Image Filter(水平數(shù)字圖像濾波器)
中文描述: 臥式數(shù)字圖像過(guò)濾器(水平數(shù)字圖像濾波器)
文件頁(yè)數(shù): 13/24頁(yè)
文件大?。?/td> 575K
代理商: LF3320
DEVICES INCORPORATED
Video Imaging Products
2-13
LF3320
Horizontal Digital Image Filter
08/16/2000
LDS.3320-N
Output Adder
The Output Adder adds the Filter A and
B outputs together when the device is in
Single Filter Mode. If 24-bit data and 12-
bit coefficients or 12-bit data and 24-bit
coefficients are desired, the LF3320 can
facilitate this by scaling the Filter B
output by 2
-12
before adding it to the
Filter A output. Bit 3 in Configuration
Register 5 determines if the Filter B
output is scaled before being added to
the Filter A output.
Rounding
The overall filter output (Single Filter
Mode) or Filter A and B outputs (Dual
Filter Mode) may be rounded by adding
the contents of one of the sixteen Filter
A or B round registers to the overall
filter, Filter A, or Filter B outputs (see
Figure 10). The Filter A round registers
are used for the overall filter (Single
Filter Mode) or Filter A (Dual Filter
Mode). The Filter B round registers are
used for Filter B (Dual Filter Mode).
Each round register is 32-bits wide and
user-programmable. This allows the
filter’s output to be rounded to any
precision required. Since any 32-bit
value may be programmed into the
round registers, the device can support
complex rounding algorithms as well as
standard Half-LSB rounding. RSLA
3-0
determines which of the sixteen
Filter A round registers are used in the
Filter A rounding circuitry. RSLB
3-0
determines which of the sixteen Filter B
round registers are used in the Filter B
rounding circuitry. A value of 0 on
RSLA/ RSLB
3-0
selects Filter A/ B
round register 0. A value of 1 selects
Filter A/ B round register 1 and so
on. RSLA/ RSLB
3-0
may be changed
every clock cycle if desired. This
allows the rounding algorithm to be
changed every clock cycle. This is
useful when filtering interleaved
data. If rounding is not desired, a
round register should be loaded with 0
and selected as the register used for
rounding. Round register loading is
discussed in the LF Interface
TM
section.
Output Select
The word width of the overall filter,
Filter A, and Filter B outputs is 32-bits.
However, only 16-bits may be sent to
DOUT
15-0
(Single or Dual Filter Modes)
and COUT
11-0
/ ROUT
3-0
(Dual Filter
Mode). The Filter A/ B select circuitry
determines which 16-bits are passed
(see Table 1). The Filter A/ B select
registers control the Filter A/ B select
circuitry. There are sixteen Filter A
and B select registers.
The Filter A select registers are used for
the overall filter (Single Filter Mode) or
Filter A (Dual Filter Mode). The Filter B
select registers are used for Filter B (Dual
Filter Mode). Each select register is 5 bits
wide and user-programmable. RSLA
3-0
determines which of the sixteen Filter A
select registers are used in the Filter A
select circuitry. RSLB
3-0
determines
which of the sixteen Filter B select
registers are used in the Filter B select
circuitry. A value of 0 on
RSLA/ RSLB
3-0
selects Filter A/ B select
register 0. A value of 1 selects Filter A/ B
select register 1 and so on.
RSLA/ RSLB
3-0
may be changed every
clock cycle if desired. This allows the
16-bit window to be changed every
clock cycle. This is useful when filtering
interleaved data. Select register load-
ing is discussed in the LF Interface
TM
section.
F
IGURE
16. F
ILTER
A
AND
B R
OUND
/S
ELECT
/L
IMIT
C
IRCUITRY
R
R
32
L
L
32
4
RSLA
3-0
R
R
32
L
L
32
4
RSLB
3-0
RND
LIMIT
32
16
RND
LIMIT
32
16
16
16
FILTER B RSL
FILTER A RSL
DATA IN
32
DATA IN
32
DATA OUT
DATA OUT
S
S
5
S
S
5
SELECT
SELECT
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