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參數(shù)資料
| 型號： | LE28FV4001CTS-20 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | EEPROM |
| 英文描述： | 4M-Bit Flash EEPROM |
| 中文描述： | 4分位閃存EEPROM |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 156K |
| 代理商： | LE28FV4001CTS-20 |
LE28FV4001CTS-20
4M-Bit Flash EEPROM
Preliminary Specifications
SANYO Electric Co., Ltd.
4/14
Command Definition
Table 3 contains a command list and a brief summary of the
commands.
The following is a detailed description of the options initiated
by each command.
The LE28FV4001C has to have the Software Data Unprotect
Sequence executed prior a Byte Program or Erase in order to
perform those functions.
Sector_Erase Operation
The Sector_Erase operation is initiated by a setup command
and an execute command. The setup command stages the device
for electrical erasing of all bytes within a sector. A sector contains
256 bytes. This sector erasability enhances the flexibility and
usefulness of the LE28FV4001C, since most applications only
need to change a small number of bytes or sectors, not the entire
chip. The setup command is performed by writing (20H) to the
device. To execute the sector-erase operation, the execute
command (D0H) must be written to the device. The erase operation
begins with the rising edge of the
WE
pulse and terminated
automatically by using an internal timer. See Figure 8 for timing
waveforms.
The two-step sequence of a setup command followed by an
execute command ensures that only memory contents within the
addressed sector are erased and other sectors are not inadvertently
erased.
Sector_Erase Flowchart Description
Fast and Reliable erasing of the memory contents within a
sector is accomplished by following the sector erase flowchart as
shown in Figure 3. The entire procedure consists of the execution
of two commands. The Sector_Erase operation will terminate after
a maximum of 4ms. A Reset command can be executed to
terminate the erase operation; however, if the erase operation is
terminated prior to the 4ms time-out, the sector may not be
completely erased. An erase command can be reissued as many
times an necessary to complete the erase operation. The
LE28FV4001C cannot be “overerased”.
Byte_Program Operation
The Byte_Program operation is initiated by writing the setup
command (10H).
Once the program setup is performed, programming is executed
by the next
WE
pulse. See Figure 6 and 7 for timing waveforms.
The address bus is latched on the falling edge of
WE
,
CE
, or
the rising edge of
OE
, whichever occurs first. The programming
operation begins with either the rising edge of
WE
,
CE
,
whichever occurs first. The programming operation is terminated
automatically by an internal timer. See the programming
characteristics and waveforms for details, Figures 4, 6 and 7.
The two-step sequence of a setup command followed by an
execute command ensures that only the addressed byte is
programmed and other bytes are not inadvertently programmed.
The Byte_Program Flow Chart Description
Programming data into the device is accomplished by following
the Byte_Program flowchart as shown in Figure 3. The
Byte_Program command sets up the byte for programming. The
address bus is latched on the falling edge of
WE
,
CE
,
whichever occurs last. The data bus is latched on the rising edge of
WE
,
CE
, whichever occurs first, and begins the program
operation. The end of write can be detected using either the
DATA
polling or Toggle bit.
Reset Operation
A Reset Command is provided as a means to safely abort the
erase or program command sequences. Following either setup
command (erase or program) with a write of (FFH) will safely
abort the operation. Memory contents will not be altered. After the
Reset command, the device returns to the read mode. The reset
command dose not enable write protect. See figure 10 for timing
waveforms.
Read Operation
The read operation is initiated by setting
CE
,
OE
and
WE
into the read mode. See Figure 5 for read memory timing
waveforms and Table 2 for the read mode. Read cycles from the
host retrieve data from the array. The device remains enabled for
read until another operating mode is accessed.
During initial power-up, the device is in the read mode and is
write protected. The device must be unprotected in order to execute
a write operation
The read operation is controlled by
OE
and
CE
at logic low.
When
CE
is high, the chip is deselected and only standby power
will be consumed.
OE
is the output control and is used to gate to
the output pins. The data bus is in a high impedance state when
either
CE
or
OE
is high.
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PDF描述 |
|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LE28FV4001M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4MEG (52488 x 8 Bits) Flash Memory |
| LE28FV4001M-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LE28FV4001R | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4MEG (52488 x 8 Bits) Flash Memory |
| LE28FV4001R-20 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4MEG (52488 x 8 Bits) Flash Memory |
| LE28FV4001R-25 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:4MEG (52488 x 8 Bits) Flash Memory |
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