- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358777 > LE28DW8102T (Sanyo Electric Co.,Ltd.) 8 Megabit FlashBank Memory LE28DW8102T PDF資料下載
參數(shù)資料
| 型號： | LE28DW8102T |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8 Megabit FlashBank Memory LE28DW8102T |
| 中文描述： | 8兆FlashBank內(nèi)存LE28DW8102T |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 338K |
| 代理商： | LE28DW8102T |
8 Megabit FlashBank Memory
LE28DW8102T
2
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.01(2/15/2000) No.xxxx-2/19
read current to the range of 1mA/MHz of Read cycle time.
If a concurrent Read while Write is being performed, the I
DD
is reduced to typically 40mA. The device exits the Auto Low
Power mode with any address transition or control signal
transition used to initiate another Read cycle, with no access
time penalty.
Read
The Read operation of the LE28DW8102T Flash banks is
controlled by CE# and OE#, a chip enable and output enable
both have to be low for the system to obtain data from the
outputs. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance state
when OE# is high. Refer to the timing waveforms for further
details (Figure 3).
When the read operation is executed without address
change after power switch on, CE# should be changed the
level high to low. If the read operation is executed after
programing , CE# should be changed the level high to low.
Write
All Write operations are initiated by first issuing the Soft-
ware Data Protect (SDP) entry sequence for Bank, Block, or
Sector Erase. Word Program in the selected Flash bank.
Word Program and all Erase commands have a fixed dura-
tion, that will not vary over the life of the device, i.e., are
independent of the number of Erase/Program cycles en-
dured.
Either Flash bank may be read to another Flash Bank during
the internally controlled write cycle.
The device is always in the Software Data Protected mode for
all Write operations Write operations are controlled by
toggling WE# or CE#. The falling edge of WE# or CE#,
whichever occurs last, latches the address. The rising edge of
WE# or CE#, whichever occurs first, latches the data and
initiates the Erase or Program cycle.
For the purposes of simplification, the following descrip-
tions will assume WE# is toggled to initiate an Erase or
Program. Toggling the applicable CE# will accomplish the
same function. (Note, there are separate timing diagrams to
illustrate both WE# and CE# controlled Program or Write
commands.)
Word Program
The Word Program operation consists of issuing the SDP
Word Program command, initiated by forcing CE# and WE#
low, and OE# high. The words to be programmed must be in
the erased state, prior to programming. The Word Program
command programs the desired addresses word by word.
During the Word Program cycle, the addresses are latched by
the falling edge of WE#. The data is latched by the rising edge
of WE#. ( See Figure 4-1 for WE# or 4-2 for CE# controlled
Word Program cycle timing waveforms, Table 3 for the
command sequence, and Figure 15 for a flowchart. )
During the Erase or Program operation, the only valid reads
from that bank are Data# Polling and Toggle Bit. The other
bank may be read.
The specified Bank, Block, or Sector Erase time is the only
time required to erase. There are no preprogramming or
other commands or cycles required either internally or
externally to erase the bank, block, or sector.
Erase Operations
The Bank Erase is initiated by a specific six-word load sequence
(See Tables 3). A Bank Erase will typically be less than 70 ms.
An alternative to the Bank Erase in the Flash bank is the Block
or Sector Erase. The Block Erase will erase an entire Block (32K
words) in typically 15 ms. The Sector Erase will erase an entire
sector (1024 words) in typically 15 ms. The Sector Erase
provides a means to alter a single sector using the Sector Erase
and Word Program modes. The Sector Erase is initiated by a
specific six-word load sequence (see Table 3).
During any Sector, Block, or Bank Erase within a bank, any
other bank may be read.
Bank Erase
The LE28DW8102T provides a Bank Erase mode, which allows
the user to clear the Flash bank to the "1"state. This is useful
when the entire Flash must be quickly erased.
The software Flash Bank Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protection operation. After the loading cycle, the device enters
into an internally timed cycle.( See Table 3 for specific codes,
Figure 5-1 for the timing waveform, and Figure12 for a flow-
chart. )
Block Erase
The LE28DW8102T provides a Block Erase mode, which allows
the user to clear any block in the Flash bank to the "1"state.
The software Block Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software Data
Protect operation. After the loading cycle, the device enters
into an internally timed Erase cycle. (See Table 3 for specific
codes, Figure 5-2 for the timing waveform, and Figure 13 for a
flowchart.) During the Erase operation, the only valid reads are
Data# Polling and Toggle Bit from the selected bank, other
banks may perform normal read.
Sector Erase
The LE28DW8102T provides a Sector Erase mode, which
allows the user to clear any sector in the Flash bank to the "1"
state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LE28DW8102T-90 | EEPROM |
| LE28F4001C | 4M-Bit (512k 】 8) Flash EEPROM |
| LE28F4001CTS | 4M-Bit (512k 】 8) Flash EEPROM |
| LE28F4001CTS-12 | 4M-Bit (512k 】 8) Flash EEPROM |
| LE28F4001M | 4 MEG (524288 words x 8 bits) Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LE28DW8102T-90 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:EEPROM |
| LE28F1101T-40 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:1M(65536words】16bits) Flash EEPROM |
| LE28F1101T-45 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:1M(65536words】16bits) Flash EEPROM |
| LE28F1101T-55 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:1M(65536words】16bits) Flash EEPROM |
| LE28F1101T-70 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:1M(65536words】16bits) Flash EEPROM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。