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參數(shù)資料
| 型號： | LE28DW1621T-80T |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 16 Megabit FlashBank Memory |
| 中文描述： | 16兆位內(nèi)存FlashBank |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 347K |
| 代理商： | LE28DW1621T-80T |
16 Megabit FlashBank Memory
LE28DW1621T-80T (Draft3)
4
SANYO Electric Co.,Ltd. Semiconductor Company 1-1-1 Sakata Oizumi Gunma Japan
R.1.20(4/27/2000) No.xxxx-4/20
Product Identification Table
Device ID codes are unique to each bank. Should a chip ID
be required, any of the bank IDs may be used as the chip ID.
While in the read software ID mode, no other operation is
allowed until after exiting these modes.
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any inadvert-
ent transient condition that apparently causes the device to
behave abnormally, e.g., not read correctly. For details, (see
Table 3 for software operation and Figures 9 for timing
waveforms.)
word load sequence is used to initiate the Program cycle,
providing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. The six-word
sequence is required to initiate any Chip, Block, or Sector Erase
operation.
The requirements for JEDEC compliant SDP are in byte format.
The LE28DW1621T is organized by word; therefore, the con-
tents of DQ
8
to DQ
15
are "Don't Care"during any SDP (3-word
or 6-word) command sequence.
During the SDP load command sequence, the SDP load cycle
is suspended when WE# is high. This means a read may occur
to any other bank during the SDP load sequence.
The bank reserve in SDP load sequence is reserved by the bus
cycle of command materialization. If the command sequence
is aborted, e.g., an incorrect address is loaded, or incorrect data
is loaded, the device will return to the Read mode within T
RC
of
execution of the load error.
Concurrent Read and Write Operations
The LE28DW1621T provides the unique benefit of being able to
read any bank, while simultaneously erasing, or programming
one other bank. This allows data alteration code to be executed
from one bank, while altering the data in another bank. The next
table lists all valid states.
Concurrent Read/Write State Table
Note: For the purposes of this table, write means to Block, Sector,
or Chip Erase, or Word Program as applicable to the
appropriate bank.
The device will ignore all SDP commands and toggling of WE#
when an Erase or Program operation is in progress. Note,
Product Identification entry commands use SDP; therefore, this
command will also be ignored while an Erase or Program,
operation is in progress.
Product Identification
The product identification mode identifies the device manufac-
turer as SANYO and provides a code to identify each bank. The
manufacturer ID is the same for each bank; however, each bank
has a separate device ID. Each bank is individually accessed
using the applicable Bank Address and a software command.
Users may wish to use the device ID operation to identifythe write
algorithm requirements for each bank. (For details, see Table 3
for software operation and Figures 8 for timing waveforms. )
1
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Figure 1 : Pin Description : TSOP-1 (12mm x 20mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
(12mm x 20mm)
TSOP-I
Normal Bend
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| LE28DW1621T | 16 Megabit FlashBank Memory |
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