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參數(shù)資料
| 型號： | LC8903 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Digital Audio Interface Receiver(數(shù)字音頻接口接收器) |
| 中文描述： | 數(shù)字音頻接口接收器（數(shù)字音頻接口接收器） |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 201K |
| 代理商： | LC8903 |
Errors
1. ERROR pin: This pin goes high when there are errors in the input data or when the PLL circuit is unlocked. When
data demodulation returns to normal, the high level is held for about 200 to 300 ms and then the ERROR pin goes
low. This time is inversely proportional to the fs of the input data.
2. Data processing when an error occurs: The table lists the data processing performed when an error occurs.
Note: Preamble detection is used to recognize PLL lock errors.
Analog Source Mode
The LC8903 and LC8903Q switch to analog source in the following two cases.
1. When analog source mode is selected by the data sent over the microprocessor interface
2. When there is no signal on the input pin selected for data demodulation
In analog source mode, the clock that runs the whole system is supplied by the crystal oscillator clock and the PLL
circuit and data demodulation are stopped. The BCLK, LRCK, CLK, OUT1 and CLKOUT2 clocks are output.
The output pins function as follows in analog source mode.
DOUT1, V/DOUT2
Data specified through the microprocessor interface is output.
ERROR
The lock error state high level is output.
SUB1, SUB2
The “#1” lock error state code is output.
DATAOUT
The lock error state low level is output.
EMPHA, V flag
The lock error state low level is output.
Microprocessor interface codes
Input codes: The code values set through the microprocessor interface are retained.
Output codes: Values identical to those for a PLL lock error are output.
Crystal Oscillator
1. The presence or absence of data is determined by an internal detection circuit. This circuit operates on either the
VCO or the crystal oscillator clock. When power is first applied, the clock is supplied from the VCO, and the
LC8903 and LC8903Q switch to the crystal oscillator if a no data state is detected. Here, if a clock signal was not
supplied from the crystal oscillator after a no data state is detected, the whole system would stop and remain in the
stopped state, since the detection circuit would not operate even if data were supplied.
2. The XIN and XOUT pins include a built-in oscillator amplifier circuit, and take on the following states when a
crystal oscillator is connected.
Note:
*
The XIN pin is pulled-up internally when the LC8903/Q is in the data present state.
No. 4542-12/15
LC8903, 8903Q
Error Type
Audio Output Data
FS Output Code
V Flag
Up to 8 consecutive parity errors
Previous data value output
Retained
Output
Nine or more consecutive
parity errors
Data with the value zero is output.
Retained
Output
PLL lock error
Data with the value zero is output.
Data is cleared and the “#1” state is
indicated.
Cleared, and a low level output.
Pin
Data Present
*
Data Absent
XIN
High
Accepts crystal oscillator input.
XOUT
Low
Outputs the inverted state of the XIN pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC8903/8903Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Interface Receiver |
| LC8903Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio |
| LC8904 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8904Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC89051V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
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