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參數(shù)資料
| 型號(hào)： | LC8903 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Digital Audio Interface Receiver(數(shù)字音頻接口接收器) |
| 中文描述： | 數(shù)字音頻接口接收器（數(shù)字音頻接口接收器） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 201K |
| 代理商： | LC8903 |
Interpretation of the D1 and D2 bits
Note: 1. The “#1” value indicates either a PLL lock error or analog source mode. In these states the data is cleared and bits D0 and D3 to D15 are all set to low.
2. D1 and D2 are in the “#1” state in the initial values of the codes immediately after the XMODE pin goes from low to high. All other codes are set to low.
3. The interval between one microprocessor data readout operation and the next must be 6 ms or longer.
FS Output Code
The SUB1 and SUB2 pins indicate the input data sampling frequency.
Note: The “#1” value indicates PLL lock error or analog source mode. When SUB1 and SUB2 have these values, the DATAOUT and EMPHA pins will
output low levels.
CD Subcode Interface
The LC8903 and LC8903Q use the SFSY, SBCK, PW and SBSY pins to output the CD subcode data. This data is the
user bits that were transferred according to the CP-1201 interface format and converted to a format that conforms to the
CP-2401 interface format. The timing is shown in the figures.
The timing of the rising and falling edges of the SFSY signal is changed according to the timing of the start bits in the
input data user bits as shown in the figure.
No. 4542-11/15
LC8903, 8903Q
Sampling frequency
32 kHz
44.1 kHz
48 kHz
#1
D1
H
L
L
H
D2
H
L
H
L
Sampling frequency
32 kHz
44.1 kHz
48 kHz
#1
SUB1
H
L
L
H
SUB2
H
L
H
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC8903/8903Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Interface Receiver |
| LC8903Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio |
| LC8904 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8904Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC89051V | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
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