參數(shù)資料
型號: LC72710LW
廠商: Sanyo Electric Co.,Ltd.
英文描述: Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder(移動FM多路廣播接收器芯片帶片上VICS譯碼器)
中文描述: 移動調(diào)頻多路廣播(DARC)接收器集成電路片VICS解碼器(移動調(diào)頻多路廣播接收器芯片帶片上VICS譯碼器)
文件頁數(shù): 5/33頁
文件大?。?/td> 168K
代理商: LC72710LW
No. 6166-5/33
LC72710W, 72710LW
[LC72710LW]
Allowable Operating Ranges: Parallel Interface
at Ta = –40 to +85°C, V
SS
= 0 V
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the “RD low-level width“ will be 280 ns (minimum).
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Address to RD setup
t
SARD
t
HARD
t
WRDL
1
t
WRDL
2
t
CYRD
t
WRDY
t
RDH
t
SAWR
t
HAWR
t
CYWR
t
WWRL
t
WDH
t
DRDY
A0/CL, A1/CE, A2/DI, A3, RD
A0/CL, A1/CE, A2/DI, A3, RD, t
WRDL
250 ns
RD
20
ns
RD to address hold
–20
ns
RD low-level width
280
ns
RD low-level width (when RDY is used)
RD
100
280
ns
RD cycle wait
A0/CL, A1/CE, A2/DI, A3, RD
150
ns
RDY width (Register read)
RDY
60
230
ns
RD data hold
RD, DATn
0
ns
Address to WR setup
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR to address hold
A0/CL, A1/CE, A2/DI, A3, WR
20
ns
WR cycle wait
A0/CL, A1/CE, A2/DI, A3, WR
150
ns
WR low-level width
WR
200
ns
WR data hold
WR, DATn
0
ns
RDY output delay
RD, RDY
0
50
ns
Corrected output RD width
t
WDRD
1
RD (BUSWD = L 8 bits)
300
ns
RD (BUSWD = H 16 bits)
540
ns
Corrected output RD width
t
WDRD
2
RD (BUSWD = L 8 bits)
100
300
ns
(when RDY is used)
RD (BUSWD = H 16 bits)
300
540
ns
RDY width (corrected output read)
t
WDRDY
RDY (BUSWD = L 8 bits)
60
230
ns
RDY ((BUSWD = H 16 bits)
300
490
ns
DACK to DREQ delay
t
DREQ
t
CYDM
t
WRDM
DREQ, DACK
260
ns
DMA cycle wait
RD, DREQ
420
ns
RD low-level width (DMA)
RD
300
ns
P
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