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參數(shù)資料
| 型號(hào)： | LC723740 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | ETR Microcontrollers(大容量電子調(diào)諧應(yīng)用的微控制器) |
| 中文描述： | 東突微控制器（大容量電子調(diào)諧應(yīng)用的微控制器） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 229K |
| 代理商： | LC723740 |
No. 5931-8/14
LC723732/40/48/56/64
Continued from preceding page.
Pin No.
Symbol
I/O
Function
Equivalent circuit
General-purpose I/O ports with shared functions as serial I/O ports
The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2 pins can be
switched to function as open drain outputs.
The IOS1 instruction is used to switch between the general-purpose I/O port and
serial I/O port functions.
When used as general-purpose I/O ports:
The pins are set to the general-purpose I/O port function using the IOS1
instruction.
The mode (input or output) is set in 1-bit units using the IOS1 instruction.
When used as serial I/O ports:
The pins are set to the serial I/O port function using the IOS1 instruction.
[Pin states when set to the serial I/O port function]
PE0, PF0, PG0 ... General-purpose I/O
PE1, PF1, PG1 ... SCK input or output
PE2, PF2, PG2 ... SO output
PE3, PF3, PG3 ... SI input
The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain
outputs with the IOS2 instruction. When using this circuit type, the external pull-up
resistors must be connected to the same power supply as that used by the IC.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
16
15
14
13
12
11
10
9
8
7
6
5
PE0
PE1/SCK2
PE2/S02
PE3/SI2
PF0
PF1/SCK1
PF2/S01
PF3/SI1
PG0
PG1/SCK0
PG2/S00
PG3/SI0
I/O
Connections for a 4.5-MHz crystal oscillator element
1
100
XIN
XOUT
I
O
Main charge pump outputs
These pins output a high level when the frequency of the local oscillator divided by n
is higher than that of the reference frequency, and they output a low level when that
frequency is lower. They go to the high-impedance state when the frequencies
match.
These pins go to the high-impedance state in backup mode, after a power on reset,
and in the PLL stopped state.
98
97
E01
E02
O
Power supply connections
The V
DD
PORT and V
SS
PORT pins mainly supply power for the peripheral I/O blocks
and the regulator.
The V
DD
PLL and V
SS
PLL pins mainly for the PLL circuits.
The V
SS
CPU pin is mainly used by the CPU block.
The V
SS
ADC pin is mainly used by the A/D converter block.
Since all the V
DD
and V
SS
pins are independent, all must be connected to the same
power supply.
39
93
4
40
81
96
V
DD
PORT
V
DD
PLL
V
SS
CPU
V
SS
PORT
V
SS
ADC
V
SS
PLL
—
Internal low voltage output
Connect a bypass capacitor to this pin.
3
V
REG
O
FM VCO (local oscillator) input
This pin is selected with CW1 in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in backup mode, after a power on reset, and in the PLL stopped
state.
95
FM
IN
I
AM VCO (local oscillator) input
This pin is selected and the band set with CW1 (b1, b0) in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in backup mode, after a power on reset, and in the PLL stopped
state.
94
AM
IN
I
b1
b0
Band
1
0
2 to 40 MHz (SW)
1
1
0.5 to 10 MHz (MW, LW)
Continued on next page.
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