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參數(shù)資料
| 型號： | LC72191JM |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning in Car Stereo Tuners |
| 中文描述： | 鎖相環(huán)頻率合成調(diào)諧器在汽車音響電子調(diào)諧 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大小： | 194K |
| 代理商： | LC72191JM |
When mode 3 is specified and data is output through DO, DO will automatically go high after data output has
completed, i.e., when CE goes low.
After that, DO goes low automatically when the IN0 signal changes state.
(That is, DO can be used to check for changes in an external signal input to IN0.)
2. When the general-purpose counter is used the DO pin can be used to check for completion of the general-purpose
counter measurement.
When CTEN is set to 1, DO going low due to changes in IN0 is disabled and DO is set high automatically.
DO is automatically set low when the general-purpose counter measurement completes.
(That is, DO can be used to check for measurement completion.)
PLL Unlock Data Read Out Procedure
The internal data UL(n) is set on the rising edge of ERROR
The ERROR data UL(n) from before the previous CE
In the example above, the data from the period between t
0
and t
1
is read out.
and reset on the rising edge of CE
rising edge can be read out in mode 3 (data output).
.
No. 3985-14/16
LC72191, 72191M, 72191JM
UL (n)
3210
0000
1000
1001
1011
1111
ERROR < 0.55 μs
→
0.55 μs
≤
ERROR < 1.11 μs
→
1.11 μs
≤
ERROR < 2.22 μs
→
2.22 μs
≤
ERROR < 3.33 μs
→
3.33 μs
≤
ERROR
→
UL0 : 1.11 μs
UL1 : 2.22 μs
UL2 : 3.33 μs
UL3 : 0.55 μs
Each bit is set to 1 according to ERROR as described above.
ERROR: the phase difference (for a 7.2 MHz crystal)
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