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參數(shù)資料
| 型號： | LC72151V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁數(shù)： | 7/29頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LC72151V |
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No. 6976-15/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
Data to control the wait time in the high-speed locking. This data is valid when the FMIN
(high-speed mode) is selected by setting DVS and SNS to 1.
*:The wait time is 20 s at a power on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
DVS
SNS
(13)
High-speed locking charge wait
time control data
CWS0, CWS1
Crystal oscillator selection data
XS = 0: 10.25 MHz
= 1: 10.35 MHz
Crystal oscillator buffer (XBUF)
XB = 0: Buffer output is turned off.
XB = 1: Buffer output is turned on.
*: XB = 0: Buffer output is turned off at a power-on reset.
R0 to R3
(18)
Crystal oscillator circuit
XS
XB
IC test control data
These bits must be set as follows during normal operation.
TEST0 = 0
TEST1 = 0
TEST2 = 0
TEST3 = 0
*: After the power-on reset, the test data is all set to zero.
(15)
IC test data
TEST0
TEST1
TEST2
TEST3
CWS1 CWS0
Wait time [s]
0
2.5
0
1
5
1
0
10
1
20
Data to control the wait time after the high-speed locking control completes till the
operation is switched to the normal PLL operation. This data is valid when the FMIN
(high-speed mode) is selected by setting DVS and SNS to 1.
During the wait time, the unlock signal is forcibly output, the sub-charge pump allows to
be operated. Thereby, reduces the locking time after switching to the normal PLL
operation.
*:The wait time is 400 s at a power on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
DVS
SNS
PDC0
PDC1
(14)
High-speed locking completion
flag output wait time control data
HSE0, HSE1
HSE1 HSE0
Wait time [s]
0
1
200
1
0
400
1
800
(16)
Reset
RST
This data resets the LC72151V.
*: After the power is first applied, the power-on reset circuit initializes the IC. However,
the data must be set to 1 to ensure the initialization.
(17)
DNC
Set data to 0
Note: After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data (RST) must be input to the IC to ensure the
initialization.
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