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參數(shù)資料
| 型號(hào)： | LC72151V |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁(yè)數(shù)： | 3/29頁(yè) |
| 文件大小： | 326K |
| 代理商： | LC72151V |
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No. 6976-11/29
LC72151V
DI control data description
No.
Control block/data
Content
Related data
This data sets the divisor for the programmable divider and P15 is the MSB of this binary
value. LSB will change according to the DVS and SNS.
*: When the LSB is P4, P0 to P3 are invalid.
Used to select programmable divider signal input pins (FMIN, AMIN) and to switch the
input frequency range.
*: When the DVS and SNS are set to 1, the high-speed locking mode is selected, the high-
speed control data becomes valid.
By setting DVS to 1 and SNS to 0 this pin enters FMIN mode, the sub-charge pump
control data is valid, the high-speed locking control data becomes invalid.
(1)
Programmable divider data
P0 to P15
DVS, SNS
This data controls the sub-charge pump.
(* : don’t care)
The sub-charge pump can be used in conjunction with the PDM1 or the PDM2 pin (main
charge pump pin) to form a high-speed locking circuit.
*: FMIN(High-speed mode): Setting DVS and SNS to 1 forces the sub-charge pump to
operate for the time set due to the high-speed locking end flag output wait time, and
allows the locking time to be reduced after switching to the normal PLL mode.
See the “Charge Pump Structure” item for details.
HSE0
HSE1
(2)
Sub-charge pump control data
PDC0, PDC1
Reference frequency selection data
Note: PLL inhibit (backup mode)
The programmable divider block is stopped, the FMIN and AMIN pins are pulled down
to ground, and the charge pump output is set to the floating state.
(3)
Reference divider data
R0 to R3
PDC1
PDC0
Sub-charge pump state
0
*
High impedance
1
Charge pump operating (at all times)
1
0
Charge pump operating (when PLL unlocked)
DVS
SNS
LSB
Set divisor (N)
1
P0
272 to 65535
1
0
P0
272 to 65535
0
1
P0
272 to 65535
0
P4
4 to 4095
DVS
SNS
Input pin
Input pin frequency range
1
FMIN
10 to 160 MHz (High-speed mode)
1
0
FMIN
10 to 160 MHz (Normal mode)
0
1
AMIN
2 to 40 MHz
0
AMIN
0.5 to 10 MHz
R3
R2
R1
R0
Reference frequency (kHz)
0
50
0
1
50
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
10
1
0
1
9
1
0
1
0
5
1
0
1
0
3
1
0
1
30
1
0
PLL inhibit + X’tal OSC stop
1
PLL inhibit
Continued on next page.
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