參數(shù)資料
型號: LC72130M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝: MFP-24
文件頁數(shù): 7/22頁
文件大小: 306K
代理商: LC72130M
Programmable Divider
Note: * Don’t care.
1. Programmable Divider Calculation Examples
FM, 50 kHz steps (DVS = 1, SNS = *, FMIN selected)
FM RF = 90.0 MHz (IF = +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 to R1 = 1, R2 to R3 = 0)
100.7 MHz (FM VCO)
÷ 25 kHz (fref) ÷ 2 (FMIN: divide-by-two prescaler) = 2014 → 07DE (HEX)
SW, 5 kHz steps (DVS = 0, SNS = 1, AMIN high speed side selected)
SW RF = 21.75 MHz (IF = +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = R2 = 0, R1 = R3 = 1)
22.2 MHz (SW VCO)
÷ 5 kHz (fref) = 4440 → 1158 (HEX)
MW, 10 kHz steps (DVS = 0, SNS = 0, AMIN low-speed side selected)
MW RF = 1000 kHz (IF = +450 kHz)
MW VCO = 1450 kHz
PLL fref = 10 kHz (R0 to R2 = 0, R3 = 1)
1450 kHz (MW VCO)
÷ 10 kHz (fref) = 145 → 091 (HEX)
No. 4973-15/22
LC72130, 72130M
DVS
SNS
Input pin
Set divisor
Actual divisor: N
Input frequency range (MHz)
A
1
*
FMIN
272 to 65535
Twice the set value
10 to 160
B
0
1
AMIN
272 to 65535
The set value
2 to 40
C
0
AMIN
4 to 4095
The set value
0.5 to 10
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