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參數(shù)資料
| 型號： | LC72130M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 10/22頁 |
| 文件大?。?/td> | 306K |
| 代理商： | LC72130M |
Unlock Detection Timing
1. Unlock Detection Determination Timing
Unlocked state detection is performed in the reference frequency (fref) period (interval). Therefore, in principle, this
determination must be performed over a period no less than the reference frequency period. However, directly
following a change to the (frequency) divisor N, that determination must be performed after at least two reference
frequency periods have passed.
Figure 1 Unlocked State Detection Timing
For example, if fref is 1 kHz, i.e., the period is 1 ms, after the divisor N is changed, unlocked state determination
must be performed after waiting 2 ms.
Figure 2 Circuit Structure
No. 4973-18/22
LC72130, 72130M
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| LC72131 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72131D | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC72131K | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72131K_12 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
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