參數(shù)資料
型號: LC72130M
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝: MFP-24
文件頁數(shù): 19/22頁
文件大?。?/td> 306K
代理商: LC72130M
Pin Functions
No. 4973-6/22
LC72130, 72130M
Symbol
Pin No.
Type
Functions
Circuit configuration
XIN
XOUT
FMIN
AMIN
CE
CL
DI
DO
VDD
1
24
15
14
3
5
4
6
16
X’tal OSC
Local oscillator
signal input
Local oscillator
signal input
Chip enable
Clock
Data input
Data output
Power supply
Crystal resonator connection
(4.5/7.2 MHz)
Serial data input: FMIN is selected when DVS is set to 1.
The input frequency range is from 10 to 160 MHz.
The signal is passed through a built-in divide-by-two
prescaler and then supplied to the swallow counter.
Although the range of divisor settings is from 272 to
65,535, the actual divisor is twice the setting since there
is also a built-in divide-by-two prescaler.
Serial data input: AMIN is selected when DVS is set to 0.
Serial data input: When SNS is set to 1:
— The input frequency range is from 2 to 40 MHz.
— The signal is supplied directly to the swallow counter.
— The range of divisor settings is from 272 to 65,535
and the actual divisor will be the value set.
Serial data input: When SNS is set to 0:
— The input frequency range is from 0.5 to 10 MHz.
— The signal is supplied directly to a 12-bit
programmable divider.
— The range of divisor settings is from 4 to 4,095 and
the actual divisor will be the value set.
Must be set high when serial data is input to the
LC72130 (DI), or when serial data is output (DO).
Used as the synchronization clock when serial data is
input to the LC72130 (DI), or when serial data is output
(DO).
Inputs serial data sent from the controller to the
LC72130.
Outputs serial data sent from the LC72130 to the
controller.
The content of the output data is determined by the
serial data DOC0 to DOC2.
The LC72130 power supply (VDD = 4.5 to 5.5 V)
The power on reset circuit operates when power is first
applied.
Continued on next page.
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PDF描述
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