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參數(shù)資料
| 型號： | LC7185-8750 |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PDIP30 |
| 封裝： | SDIP-30 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 152K |
| 代理商： | LC7185-8750 |
Allowable Operating Conditions at Ta = –40 to +85°C, VSS =0 V
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
VDD
5.0
8.0
V
Input high-level voltage
VIH1
Pins HOLD, TX
0.7VDD
12
V
VIH2
Pin INIT
3.2
VDD
V
VIH3
Pins KI1, KI2, KI3, KI4
0.6VDD
VDD
V
Input low-level voltage
VIL1
Pins HOLD, TX
0
0.3VDD
V
VIL2
Pin INIT
0
1.3
V
VIL3
Pins KI1, KI2, KI3, KI4
0
0.4VDD
V
Output voltage
VOUT1
Pins SA, SB, SC, SD, SE, SF, SG, D1, D2
0
13
V
VOUT2
Pins UL, BEEP
08
V
Input frequency
fIN1
Pin XIN (sine wave, capacitor coupled)
1.0
10.24
15
MHz
fIN2
Pin PIN (sine wave, capacitor coupled)
10
30
MHz
Input amplitude
VIN1
Pin XIN (sine wave, capacitor coupled)
0.5
1.5
Vrms
VIN2
Pin PIN (sine wave, capacitor coupled)
0.15
1.5
Vrms
Required oscillating
frequency
X’tal
Pins XIN, XOUT (CI
% 50 )
5.0
10.24
15
MHz
Electrical Characteristics at under allowable operating conditions
Parameter
Symbol
Conditions
min
typ
max
Unit
Internal feedback resistance
Rf1
Pin XIN
1.0
M
Rf2
Pin PIN
500
k
Pull-down resistor
RpdN
Pins KI1, KI2, KI3, KI4, TEST
30
50
70
k
Input high-level current
IIH1
Pins HOLD, TX VI =12V
5.0
A
IIH2
Pin INIT VI =VDD
5.0
A
IIH3
Pin XIN VI =VDD
25
A
IIH4
Pin PIN VI =VDD
50
A
Input low-level current
IIL1
Pins HOLD, TX VI =VSS
5.0
A
IIL2
Pin INIT VI =VSS
5.0
A
IIL3
Pin XIN VI =VSS
25
A
IIL4
Pin PIN VI =VSS
50
A
Output high-level voltage
VOH1
Pins KO1, KO2, KO3 IO =1mA
VDD–2.0 VDD–1.0 VDD–0.5
V
VOH2
Pin PD IO = 0.5 mA
VDD–1.0
V
Output low-level voltage
VOL1
Pins KO1, KO2, KO3 IO =20A
0.6
1.0
1.4
V
VOL2
Pin PD IO = 0.5 mA
1.0
V
VOL3
Pin BEEP IO =2mA
1.0
V
VOL4
Pins SA, SB, SC, SD, SE, SF, SG
IO =20mA
1.0
V
VOL5
Pins D1, D2 IO =5mA
1.0
V
VOL6
Pin UL IO =10mA
1.0
V
Output leakage current
IOFF1
Pins SA, SB, SC, SD, SE, SF, SG, D1, D2
VO =13V
5.0
A
IOFF2
Pins UL, BEEP VO =8V
5.0
A
High-level tristate leakage
current
IOFFH
Pin PD VO =VDD
0.01
10.0
nA
Low-level tristate leakage
current
IOFFL
Pin PD VO =VSS
0.01
10.0
nA
Supply current
IDD1
Normal mode
*1 (PLL operates)
510
mA
IDD2
Hold mode VDD = 3.2 V
*2 (memory backup)
VDD = 8.0 V
5
15
A
*1: fIN2=20 MHz (PIN)
VIN2= 0.15 Vrms
X’tal = 10.240 MHz
TX = HOLD = INIT = VDD
Other inputs = VSS
Other outputs = open
*2: HOLD = VSS
TX = INIT = VDD
Other inputs = VSS
Other outputs = open
Note: Be careful that the dielectric strength of pins SA, SB, SC, SD, SE, SF, D1, D2, UL, BEEP are weak.
LC7185-8750
No. 3356-2/12
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