參數(shù)資料
型號: LC7185-8750
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 30 MHz, PDIP30
封裝: SDIP-30
文件頁數(shù): 11/12頁
文件大?。?/td> 152K
代理商: LC7185-8750
3.
Presetting channels
.
First select the channel to be preset, then hold down the ME key and press the preset memory key (M1 to M5) to
which you would like to assign the current channel.
In the following cases, a channel will not be preset:
.
M1 to M5 is pressed and in the memory preset mode.
.
Emergency channels CH9 or CH19 are currently selected.
.
The TX line is asserted.
.
The PA switch is turned on (PA mode).
.
The HOLD line is asserted (hold mode).
Even if the above key operations are not performed, the preset mode will be canceled automatically after 9 seconds.
.
There are two different display modes as shown below.
Mode 1 (without diode)
The current channel is displayed throughout the preset process.
Example: Display 15
15
Key
ME
M1
Mode 2 (with diode)
When the ME key is held down, ‘‘PE’’ is flashed on the display, indicating that presetting is possible. Once a
preset memory key (M1 to M5) is pressed, the key mnemonic (‘‘P1’’ to ‘‘P5’’) is displayed for 400 ms before the
current channel is redisplayed.
Example: Display 15
→ PE → P1 → 15
Key
ME
M1
400 ms
.
Note that if two or more keys are pressed at the same time, priority is assigned as follows:
M1>M2>M3>M4>M5
(6) Beep-tone Control Output (BEEP pin)
After each of the following events, the BEEP line is asserted for 50 ms:
.
A reset, such as a battery replacement (INIT = 0)
.
Any key press associated with the channel memory
.
Any emergency channel switch activation
.
A new channel is selected
.
Leaving hold mode
(7) Unlock Detected Output (UL pin)
In the following cases, the UL line is asserted.
.
When the phase difference between the programmable and reference divider outputs exceeds 3.2 s, the UL line is held low
for 6 ms after the last out-of-range phase sample is detected, as shown below.
.
After a new transmit/receive or channel selection, the UL line is asserted for 25 ms.
.
While the PA switch is turned on, the UL line is asserted during PA mode.
.
The UL pin is open while the device is in the PLL LOCK state (when the phase difference is < 3.2 s).
Phase
difference
pin
LC7185-8750
No. 3356-8/12
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