參數(shù)資料
型號: LC5256MB-5F256I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 43/99頁
文件大?。?/td> 0K
描述: IC XPLD 256MC 5NS 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPLD® 5000MB
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 2.3 V ~ 2.7 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 256
輸入/輸出數(shù): 141
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
44
ispXP sysCONFIG Port Timing Specifications
Symbol
Timing Parameter
Min.
Max.
Units
sysCONFIG Write Cycle Timing
tSUCS
Input setup time of CS to CCLK rise
10
ns
tHCS
Hold time of CS to CCLK rise
1
ns
tSUWD
Input setup time of write data to CCLK rise
10
ns
tHWD
Hold time of write data to CCLK rise
0
ns
tPRGM
Low time to reset device SRAM
5
50
ns
tDINIT
INIT delay time
5
ms
tIODISS
User I/O disable
ns
tIOENSS
User I/O enable
ns
tWH
Write clock High pulse width
18
ns
tWL
Write clock Low pulse width
18
ns
fMAXW
Write fMAX
—27
MHz
sysCONFIG Read Cycle Timing
tHREAD
Hold time of READ to CCLK rise
1
ns
tSUREAD
Input setup time of READ High to CCLK rise
15
ns
tRH
READ clock high pulse width
18
ns
tRL
READ clock low pulse width
18
ns
fMAXR
Read fMAX
—27
MHz
tCORD
Clock to out for read data
25
ns
SELECT
DEVICES
DISCONTINUED
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