參數(shù)資料
型號(hào)： LC5256MB-5F256I
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 10/99頁(yè)
文件大?。?/td> 0K
描述： IC XPLD 256MC 5NS 256FPBGA
標(biāo)準(zhǔn)包裝： 90
系列： ispXPLD® 5000MB
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 5.0ns
電壓電源 - 內(nèi)部： 2.3 V ~ 2.7 V
邏輯元件/邏輯塊數(shù)目： 8
宏單元數(shù)： 256
輸入/輸出數(shù)： 141
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
14
CAM Mode
In CAM Mode the multi-function array is configured as a Ternary Content Addressable Memory (CAM). CAM
behaves like a reverse memory where the input is data and the output is an address. It can be used to perform a
variety of high-performance look-up functions. As such, CAM has two modes of operation. In write or update mode
the CAM behaves as a RAM and data is written to the supplied address. In read or compare operations data is sup-
plied to the CAM and if this matches any of the data in the array the Match and Multiple Match (if there is more than
one match) flags are set to true and the lowest address with matching data is output. The CAM contains 128
entries of 48 bits. Figure 13 shows the block diagram of the CAM.
To further enhance the flexibility of the CAM a mask register is available. If enabled during updates, bits corre-
sponding with those set to 1 in the mask register are not updated. If enabled during compare operations, bits corre-
sponding to those set to 1 in the mask register are not included in the compare. A write don’t care signal allows
don’t cares to be programmed into the CAM if desired. Like other write operations the mask register controls this.
The write/comp data, write address, write enable, write chip select, and write don’t care signals are synchronous.
The CAM Output signals, match flag, and multimatch flag can be synchronous or asynchronous. The Enable mask
register input is not latched but must meet setup and hold times relative to the write clock. All inputs must use the
same clock and clock enable signals. All outputs must use the same clock and clock enable signals. Reset is com-
mon for both inputs and outputs. Table 9 shows the allowable sources for clock, clock enable, and reset for the var-
ious CAM registers.
Figure 13. CAM Mode
Table 9. Register Clocks, Clock Enables, and Initialization in CAM Mode
Register
Input
Source
Write data, Write address,
Enable mask register, Write
enable, write chip select, and
write don’t care, CAM Output,
Match, and Multimatch
Clock
CLK or one of the global clocks (CLK0 - CLK3). Each of these signals can
be inverted if required.
Clock Enable
WE or one of the global clocks (CLK1 - CLK 2). Each of these signals can
be inverted if required.
Reset
Created by the logical OR of the global reset signal and RST. RST is routed
by the multifunction array from GRP, with inversion if desired
‘
68 Inputs
From
Routing
Write Enable (WE)
En Mask Reg (EN_MASK)
Reset (RST)
Write Chip Sel (WCS[0:1])
CLK (CLK)
Clock Enable (CE)
Write/Comp Data
(WD[0:31])
128X48
CAM
Write Address
(WAD[0:6])
WR Mask Reg (WR_MASK)
WR don t care (WR_DC)
RESET
CLK0
CLK3
CLK1
CLK2
CAM
Output
CO[0:6]
Match
Out
MATCH
Multi-
match
Out
MUL_MATCH
SELECT
DEVICES
DISCONTINUED
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