參數(shù)資料
型號: LC07410LP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 5 X 5 MM, VQLP-40
文件頁數(shù): 8/35頁
文件大小: 430K
代理商: LC07410LP
LC07410LP
No.A1207-16/35
Relation Between Output level and Recovery Speed (FR,THR)
FR value is shown by inclination (FS/s) of the shape of recovery waves. (FS=Full Scale=0dBFS)
Description of ALC/Limiter (automatic level control) operation
Note: Whatever is contained inside the parentheses “ ” is applicable in the PB-ALC mode.
The amplifier gain “digital volume value” of the PGA (programmable gain amplifier) is automatically adjusted so that
the A/D converter output audio level “digital volume output” is set to the ALC value “ALC_VAL [2:0]”. The PGA
“digital volume” gain can be varied in the -14dB to +34dB range. The maximum value “ALC_VMAX [5:0]” can be set
in this variable range.
ALC settings
Power-saving function
When [PGA_PDX] is 0, the ALC circuit and PGA circuit are set to power down mode.
Manual function (ALC OFF)
At REC_ALC=PB_ALC=0, it become manual mode.
PGA gain is fixed by value of ALC_GAIN [5:0]
Digital volume value is fixed by EVR_GAIN [6:0]
System operation
ALC is performed by feeding back the A/D converter “digital volume” data. Accordingly, configure the settings
as shown in the table below in order for the ALC functions to be activated.
(1) Attack operations
When the ADC “digital volume” output exceeds the ALC limiter level, ALC_VAL[2:0], the PGA gain “digital
volume value” is lowered. When the rate of gain attenuation is ALC_THA[2:0] or more, ALC_FA1[1:0] results,
but when the value is less than ALC_THA[2:0], ALC_FA2[1:0] results.
When zero-cross detection ALC_ZCD is set to 1, the gain attenuation from zero-cross to zero-cross is limited by
the limit value ALC_TLIM[1:0].
Mode
Resister
REC-ALC
PB-ALC
PGA_PDX
1
0
ADC_PDX
1
x
DAC_PDX
x
1
REC_ALC
1
0
PB_ALC
0
1
Signal after
ADC
ALC_VAL
THR2
THR1
FR2
FR1
FR3
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