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參數(shù)資料
| 型號： | LC07410LP |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 5 X 5 MM, VQLP-40 |
| 文件頁數(shù)： | 10/35頁 |
| 文件大?。?/td> | 430K |
| 代理商： | LC07410LP |
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LC07410LP
No.A1207-18/35
Noise gate function
The noise gate function is enabled when NGEN is 1. This function cannot be used during PB-ALC mode.
If the PGA input level continues at or below NGTH[2:0] for the period NGDT[1:0], the volume after ADC output is
decreased from 0dB to approximately -35dB at the rate NGDT[1:0].
If the PGA input level rises to NGTH+6dB or more, the volume after ADC output is increased from approximately
-35dB to 0dB at the rate NGRT[1:0].
ADC
PGA output undergoes AD conversion and is output as 16-bit serial audio data. The three formats, I2S, left justified,
and right justified are supported.
If ADC_PDX is set to 0, the ADC block is powered down. An interval of 64/fs is used as the ADC initialization
interval (initialization + data delay) from the point power down is canceled. When power is turned on, initialization is
required when switching the system clock.
A digital HPF for canceling DC offset is built-in. The cut-off frequency, fc, is 1.85Hz (@fs=48kHz).
The full-scale voltage (0dBFS) is 0.6*VDDA.
DAC
16-bit serial audio data undergoes DA conversion. The three formats, I2S, left justified, and right justified are
supported.
If DAC_PDX is set to 0, the DAC block is powered down. An interval of 58/fs is used as the DAC initialization
interval (initialization + data delay) from the point power down is canceled. When power is turned on, initialization is
required when switching the system clock.
The full-scale voltage (0dBFS) is 0.6*VDDA.
Input
Silent detection thresh
Output
Noise gate: Invalid
Noise gate: Valid
Amplitude detecting phase
VOL gain
Silent detection thresh
Return level of silent detection thresh
Silent detection time
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