參數(shù)資料
型號(hào)： LAN91C96ITQFP
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝： 1 MM THICKNESS, TQFP-100
文件頁(yè)數(shù)： 40/110頁(yè)
文件大?。?/td> 655K
代理商： LAN91C96ITQFP
Non-PCI Single-Chip Full Duplex Ethernet Controller
Rev.
11/18/2004
Page 40
SMSC DS – LAN91C96I
DATASHEET
SOFT_RST - Software activated Reset. Active high. Initiated by writing this bit high and terminated by
writing the bit low. The LAN91C96I configuration is not preserved, except for Configuration, Base, and IA0-
5 Registers. The EEPROM in Local Bus mode is not reloaded after software reset.
FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times. Otherwise
recognizes a receive frame as soon as carrier sense is active.
STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory
following the packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes idle.
Defaults low on reset.
ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear
accepts only the multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames.
Change vs. LAN91C92: Does not receive its own transmission when not in full duplex(FDUPLX)!.
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 1532 bytes. The
frame will not be received. The bit is cleared by RESET or by the CPU writing it low.
I/O SPACE - BANK0
OFFSET
6
NAME
TYPE
SYMBOL
ECR
COUNTER REGISTER
READ ONLY
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register, and do not wrap around beyond 15.
NUMBER OF EXC. DEFERRED TX
0
MULTIPLE COLLISION COUNT
0
NUMBER OF DEFERRED TX
0
SINGLE COLLISION COUNT
0
0
0
0
0
0
0
0
0
0
0
0
0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS
REGISTER bit description, occurs. Note that the counters can only increment once per enqueued transmit
packet, never faster, limiting the rate of interrupts that can be generated by the counters. For example if a
packet is successfully transmitted after one collision the SINGLE COLLISION COUNT field is incremented
by one. If a packet experiences between 2 to 16 collisions, the MULTIPLE COLLISION COUNT field is
incremented by one.
If a packet experiences deferral the NUMBER OF DEFERRED TX field is incremented by one, even if the
packet experienced multiple deferrals during its collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no
transmit interrupts are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
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