參數資料
型號: LAN91C96ITQFP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 1 MM THICKNESS, TQFP-100
文件頁數: 28/110頁
文件大小: 655K
代理商: LAN91C96ITQFP
Non-PCI Single-Chip Full Duplex Ethernet Controller
Rev.
11/18/2004
Page 28
SMSC DS – LAN91C96I
DATASHEET
5.3
Reset Logic
The pins and bits involved in the different reset mechanisms are:
RESET - Input Pin
SRESET - Soft Reset bit in ECOR, or the SRESET bit
SOFT RST - EPH Soft Reset bit in RCR
Table 5.4 – Reset Logic
RESETS THE FOLLOWING FUNCTIONS
SAMPLES
LOCAL BUS
MODE
Yes
No
TRIGGERS
EEPROM
READ
Yes
Yes
RESET pin
ECOR
Register
SRESET bit
All internal logic
The Ethernet controller function except for
the bit itself. Setting this bit also lowers
the nIREQ/READY line. When cleared,
the nIREQ/READY line is raised.
The Ethernet controller itself except for
the IA, CONF and BASE registers.
SOFT RST
No
No
5.4
Power Down Logic States
Tables Table 5.5 and Table 5.6 describe the power down states of the LAN91C96I. The pins and bits
involved in power down are:
1.
2.
3.
4.
PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).
Pwrdwn bits in ECSR
Enable Function bit in ECOR
PWRDN - Legacy power down bit in Control Register.
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