參數(shù)資料
型號: LAN91C96ITQFP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 1 MM THICKNESS, TQFP-100
文件頁數(shù): 15/110頁
文件大?。?/td> 655K
代理商: LAN91C96ITQFP
Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I
Page 15
Rev. 11/18/2004
DATASHEET
Chapter 4
Description of Pin Functions
PIN NO.
TQFP
93
QFP
95
PIN NAME
nROM
TYPE
I/O4 with
pullup
DESCRIPTION
This pin is sampled at the end of RESET. For Local Bus
operation this pin is left open and it is used as a ROM chip
select output that goes active when nMEMR is low and the
address bus contains a valid ROM address. In Local Bus
mode the LAN91C96I is pin compatible with the LAN91C92
and LAN91C94
Input address lines 0 through 9.
26-28
30-36
37
39
40-46
28,29,
30, 32-38
A0-9
I
**
I
I
I
**
I with
pullup
I with
pullup
**
39
41
A10/nFWE
A11/nFCS
A12-18
Local Bus - Input address line 10.
Local Bus - Input address line 11.
Input address lines 12 through 18.
42-48
47
49
A19/nCE1
Local Bus - Input address line 19.
52
54
AEN/
nREG/
nAS
nSBHE/
nCE2
Local Bus - Address enable input. Used as an address
qualifier. Address decoding is only enabled when AEN is low.
24
26
I with
pullup
**
OD24
with
pullup
I/O24
Local Bus - Byte High Enable input. Asserted (low) by the
system to indicate a data transfer on the upper data byte.
53
55
IOCHRDY/
nWAIT
Local Bus - Output. Optionally used by the LAN91C96I to
extend host cycles.
55-58
60-63 7-
10 12-15
57-60,
62-65,
9-12,
14-17
67
D0-15
Bi-directional. 16 bit data bus used to access the LAN91C96I
internal registers. The data bus has weak internal pullups.
Supports direct connection to the system bus without
external buffering.
65
RESET
IS with
pullup
**
IS with
pullup
**
O24
Input. Active high Reset. This input is not considered active
unless it is active for at least 100ns to filter narrow glitches.
25
27
BALE/nWE
Local Bus - Input. Address strobe. For systems that require
address latching, the falling edge of BALE latches address
lines and nSBHE.
17
19
INTR0/
nIREQ/
INTR
Local Bus - Active high interrupt signal. The interrupt line
selection is determined by the value of INT SEL1-0 bits in the
Configuration Register. This interrupt is tri-stated when not
selected.
Local Bus - Output. Active high interrupt signal. The interrupt
line selection is determined by the value of INT SEL1-0 bits
in the Configuration Register. This interrupt is tri-stated when
not selected.
Local Bus - Outputs. Active high interrupt signals. The
interrupt line selection is determined by the value of INT
SEL1-0 bits in the Configuration Register. These interrupts
are tri-stated when not selected.
18
20
INTR1/
nINPACK
O24
20
22
INTR2
O24
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