參數(shù)資料
型號: LAN91C96I-MU
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 1 MM THICKNESS, LEAD FREE, TQFP-100
文件頁數(shù): 4/110頁
文件大?。?/td> 655K
代理商: LAN91C96I-MU
Non-PCI Single-Chip Full Duplex Ethernet Controller
Rev.
11/18/2004
Page 4
SMSC DS – LAN91C96I
DATASHEET
Table of Contents
Chapter 1
Chapter 2
Chapter 3
3.1
Chapter 4
4.1
Chapter 5
5.1
5.2
5.3
5.4
Chapter 6
Chapter 7
7.1
7.2
7.2.1
Chapter 8
8.1
8.2
8.3
8.4
8.5
8.6
Chapter 9
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
Chapter 10
10.1
10.2
Chapter 11
11.1
11.2
Chapter 12
General Description.............................................................................................................6
Overview...............................................................................................................................7
Pin Configurations.............................................................................................................10
Local Bus vs. Pin Requirements .......................................................................................................13
Description of Pin Functions.............................................................................................15
Buffer Symbols..................................................................................................................................18
Functional Description.......................................................................................................20
Buffer Memory...................................................................................................................................21
Interrupt Structure .............................................................................................................................27
Reset Logic........................................................................................................................................28
Power Down Logic States.................................................................................................................28
Packet Format in Buffer memory for Ethernet...............................................................30
Registers Map in I/O Space...............................................................................................33
I/O Space Access..............................................................................................................................34
I/O Space Registers Description.......................................................................................................35
Bank Select Register..............................................................................................................................35
Theory of Operation ..........................................................................................................59
Typical Flow Of Events For Transmit (Auto Release =0)..................................................................61
Typical Flow of Events for Transmit (Auto Release = 1)...................................................................62
Typical Flow Of Events For Receive.................................................................................................63
Memory Partitioning ..........................................................................................................................69
Interrupt Generation..........................................................................................................................69
Power Down......................................................................................................................................71
Functional Description of the Blocks................................................................................73
Memory Management Unit................................................................................................................73
Arbiter................................................................................................................................................73
Bus Interface .....................................................................................................................................74
Wait State Policy ...............................................................................................................................74
Arbitration Considerations.................................................................................................................75
DMA Block.........................................................................................................................................75
Packet Number FIFOs.......................................................................................................................76
CSMA Block ......................................................................................................................................77
Network Interface..............................................................................................................................79
10BASE-T ......................................................................................................................................79
AUI .................................................................................................................................................79
Physical Interface...........................................................................................................................80
Transmit Functions.........................................................................................................................80
Transmit Drivers.............................................................................................................................80
Receive Functions..........................................................................................................................80
Board Setup Information...............................................................................................82
Diagnostic LEDs.............................................................................................................................83
Bus Clock Considerations..............................................................................................................83
Operation Description....................................................................................................85
Maximum Guaranteed Ratings*.....................................................................................................85
DC Electrical Characteristics .........................................................................................................86
Timing Diagrams ............................................................................................................92
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