參數(shù)資料
型號(hào): LAN91C96I-MU
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 1 MM THICKNESS, LEAD FREE, TQFP-100
文件頁數(shù): 27/110頁
文件大?。?/td> 655K
代理商: LAN91C96I-MU
Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I
Page 27
Rev. 11/18/2004
DATASHEET
Table 5.1 - LAN91C96I Address Space
SIGNALS
USED
nIORD/
nIOWR
LOCAL
BUS
Y
ON-CHIP
DEPTH
WIDTH
Ethernet I/O
space (1)
Y
16 locations
8 or 16
bits
Table 5.2 - Bus Transactions In Local Bus Mode
A0
0
NSBHE
X
D0-7
Even byte
D8-15
-
8 BIT MODE
((nEN16=1)
(16BIT=0))
16 BIT MODE
otherwise
1
0
X
0
Odd byte
Even byte
-
Odd byte
0
1
1
1
0
1
Even byte
-
-
Odd byte
Invalid cycle
16BIT:
CONFIGURATION REGISTER bit 7
IOis8:
CSR register bit 5
nEN16:
pin nEN16
8 Bit mode:
((IOis8 = 1) + (nMIS16 = 1)
5.2
Interrupt Structure
The Ethernet interrupt is conceptually equivalent to the LAN91C94 interrupt line, it is the or function of all
enabled interrupts within the Ethernet core. The enabling, reporting, and clearing of these sources is
controlled by the ECOR register. The interrupt structure is similar for Local Bus modes with the following
exceptions:
Table 5.3 – Interrupt Merging
FUNCTION
LOCAL BUS MODE
Interrupt Output
Ethernet Interrupt Source
INTR0-3
OR function of all interrupt bits specified in the Interrupt Status Register
ANDed with their respective Enable bits
Not Applicable in Local Bus mode
Intr bit in ECSR
Ethernet Interrupt Enable
Ethernet Interrupt Status Bit
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