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參數(shù)資料
| 型號： | LAN91C96(100TQFP) |
| 英文描述： | LAN Node Controller |
| 中文描述： | 網(wǎng)絡(luò)節(jié)點控制器 |
| 文件頁數(shù)： | 36/55頁 |
| 文件大?。?/td> | 482K |
| 代理商： | LAN91C96(100TQFP) |
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FEAST Fast Ethernet Controller
for PCMCIA and Generic 16-Bit Applications
SMSC DS – LAN91C110 REV. B
Page 36
Rev. 09/05/02
Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER
MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX packet
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed until a
transmit interrupt is generated.
5
The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duplex mode
only) state.
6
a) Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FIFO into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
b) If a TX failure occurs on any packets, TX INT
is generated and TXENA is cleared,
transmission sequence stops. The packet
number of the failure packet is presented at the
TX FIFO PORTS Register.
7 a) SERVICE INTERRUPT - Read Interrupt Status
Register. If it is a transmit interrupt, read the TX
FIFO Packet Number from the FIFO Ports
Register. Write the packet number into the Packet
Number Register. The corresponding status word
is now readable from memory. If status word
shows successful transmission, issue RELEASE
packet number command to free up the memory
used by this packet. Remove packet number
from completion FIFO by writing TX INT
Acknowledge Register.
b) Option 1) Release the packet.
Option 2) Check the transmit status in the EPH
STATUS Register, write the packet number of
the current packet to the Packet Number
Register, re-enable TXENA, then go to step 4 to
start the TX sequence again.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LAN91C96I | 制造商:SMSC 制造商全稱:SMSC 功能描述:NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER |
| LAN91C96I_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Non-PCI Single-Chip Full Duplex Ethernet Controller |
| LAN91C96IMS | 制造商:Microchip Technology Inc 功能描述: |
| LAN91C96I-MS | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C96I-MU | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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