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參數(shù)資料
| 型號： | LA7265W |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Single-Chip Black and White CCD Camera Signal Processing IC(單片黑白CCD照相機信號處理芯片) |
| 中文描述： | 單芯片黑白CCD攝像機信號處理集成電路（單片黑白防治荒漠化公約照相機信號處理芯片） |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 355K |
| 代理商： | LA7265W |
Continued from preceding page.
Unit (resistance:
), I: input, O: output, B: I/O, P: power supply
Function
No. 4850-18/24
LA7265W
Continued on next page.
Pin No.
Symbol
I/O
Equivalent circuit
42
43
44
45
46
47
48
CLP0
VIDEO-GND
DS1
DS2
SH-V
CC
SH-P
SLICE
I
P
I
I
P
I
I
CCD signal clamp pulse input. The CCD signal input to pin 1 is
clamped to the prescribed voltage with the OPB timing. This pin inputs
that clamp pulse (
), and normally can be shared with pin 41.
Ground for the video system.
Data timing sampling pulse input. This signal is divided into two paths
to perform CDS (correlation dual sampling) on the sliced CCD signal.
In the first path, the data level is sampled and held (SH1) with the
data timing. This pin is the sampling pulse (
function.
) input pin for that
Pre-charge timing sampling pulse input. In the second sliced CCD
signal path, the precharge level is sampled and held (SH2) with the
precharge timing. This pin is the sampling pulse (
that function. Next, this sampled and held signal is once again
sampled and held (SH3), here, by DS1 (the data timing sampling
pulse). Finally, the reset noise for each pixel is taken up by
subtracting these two sampled and held signals by a mixing amplifier.
) input pin for
CDS system V
CC
. Apply 5 V and insert a 0.1 μF capacitor between
this pin and ground.
This pin controls the charge/discharge speed of the SH2 and SH3
circuits. Pin usage is identical to that for pin 3.
CCD signal level control. Slices the saturation level of the CCD signal
that was OPB clamped. The possible slice levels are as follows:
Pin 48 = 0 V:........................about 1.5 V
Pin 48 = open: .....................about 1.1 V
Pin 48 = 5 V:........................about 0.5 V
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