參數(shù)資料
型號: LA7265W
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip Black and White CCD Camera Signal Processing IC(單片黑白CCD照相機信號處理芯片)
中文描述: 單芯片黑白CCD攝像機信號處理集成電路(單片黑白防治荒漠化公約照相機信號處理芯片)
文件頁數(shù): 14/24頁
文件大?。?/td> 355K
代理商: LA7265W
Continued from preceding page.
Unit (resistance:
), I: input, O: output, B: I/O, P: power supply
Function
No. 4850-14/24
LA7265W
Continued on next page.
Pin No.
Symbol
I/O
Equivalent circuit
21
22
23
24
25
PED
W. CLIP
Y2. OUT
Y2. IN
Y2D. IN
I
I
O
I
I
Setup control. The setup level can be controlled by using this pin to
control the level of the pedestal that is added with the timing of the
blanking pulse input to pin 38.
Pin 21 = 0 V:........................Setup level = –120 mV
Pin 21 = open: .....................Setup level = 95 mV
Pin 21 = 5 V:........................Setup level = 240 mV
Saturation level control. The LA7265W white clips the signal to which
pedestal has been added at pin 21. This pin adjusts the white
clipping level.
Pin 22 = 0 V:........................Clipping at about 0.9 V
Pin 22 = open: .....................Clipping at about 1.5 V
Pin 22 = 5 V:........................Clipping at about 2.0 V
Outputs the signal that has passed through the Y gain control. (See
the description of pin 17.) Normally, this output is input to pin 24 (25)
through a coupling capacitor. However, it is input to pin 29 through a
coupling capacitor when aperture correction is not used.
Original signal input. Input the
γ
corrected signal through a coupling
capacitor. OPB clamping is applied at the input stage, clamping at
about 1.8 V. The clamping pulse signal is input to pin 40.
Input for the 1H delayed signal used for interpolation. When a low
resolution CCD device (e.g., about 60,000 pixels) is used and 1H
interpolation is desired, use a 1H delay line and input the 1H delayed
signal through a coupling capacitor. OPB clamping is applied at the
input stage, clamping at about 1.8 V. Leave this pin open when 1H
interpolation is not required. Input the clamping pulse signal to pin 40.
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