參數(shù)資料
型號(hào): LA4128ZC-75TN100E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 17/42頁
文件大?。?/td> 0K
描述: IC CPLD 128MACROCELLS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: LA-ispMACH
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
宏單元數(shù): 128
輸入/輸出數(shù): 64
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
24
Boundary Scan Waveforms and Timing Specications
Symbol
Parameter
Min.
Max.
Units
tBTCP
TCK [BSCAN test] clock cycle
40
ns
tBTCH
TCK [BSCAN test] pulse width high
20
ns
tBTCL
TCK [BSCAN test] pulse width low
20
ns
tBTSU
TCK [BSCAN test] setup time
8
ns
tBTH
TCK [BSCAN test] hold time
10
ns
tBRF
TCK [BSCAN test] rise and fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to valid output
10
ns
tBTOZ
TAP controller falling edge of clock to data output disable
10
ns
tBTVO
TAP controller falling edge of clock to data output enable
10
ns
tBTCPSU
BSCAN test Capture register setup time
8
ns
tBTCPH
BSCAN test Capture register hold time
10
ns
tBTUCO
BSCAN test Update reg, falling edge of clock to valid output
25
ns
tBTUOZ
BSCAN test Update reg, falling edge of clock to output disable
25
ns
tBTUOV
BSCAN test Update reg, falling edge of clock to output enable
25
ns
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