tBSR GLB PT Set/Reset Delay — " />
參數(shù)資料
型號(hào): LA4128ZC-75TN100E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 15/42頁
文件大?。?/td> 0K
描述: IC CPLD 128MACROCELLS 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: LA-ispMACH
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 7.5ns
電壓電源 - 內(nèi)部: 1.7 V ~ 1.9 V
宏單元數(shù): 128
輸入/輸出數(shù): 64
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
Lattice Semiconductor
LA-ispMACH 4000V/Z Automotive Family Data Sheet
22
tBSR
GLB PT Set/Reset Delay
1.83
1.83
ns
tPTSR
Macrocell PT Set/Reset Delay
3.41
2.72
ns
tGPTOE
Global PT OE Delay
5.58
3.50
ns
tPTOE
Macrocell PT OE Delay
4.28
2.00
ns
Timing v.3.2
Note: Internal Timing Parameters are not tested and are for reference only. Refer to the Timing Model in this data sheet for further details.
LA-ispMACH 4000V/Z Internal Timing Parameters (Cont.)
Over Recommended Operating Conditions
Parameter
Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
Units
Min.
Max.
Min.
Max.
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