LA17000M
No. 6522-22/54
Continued from preceding page.
No.
Control block/Data
Description
Related data
Unlock detection data
This data selects the phase error (E) detection width that is used for evaluating
PLL lock.
If a phase error that exceeds the E detection width in the following table is
generated, the signal is deemed to be unlocked. When the signal is unlocked,
the detection pin (DO or I/O-5) goes low.
UL1, UL0
This is the crystal oscillator selection data.
* When a power-on reset is executed, 10.25 MHz is selected.
Crystal oscillator buffer (XBUF) output control data.
XB = 0: Buffer output: OFF (This mode is selected when a power-on reset is
executed.)
XB = 1: Buffer output ON
* For FM reception (using the PD0 pin), XBUF output must be off.
This data controls the phase comparator dead zone.
When a power-on reset is executed, DZA is selected.
This data is used to force the charge pump output to the low level (VSS level).
DLC = 1: Low level
= 0: Normal operation
* If a deadlock occurs because the VCO control voltage (Vtune) is 0 V and VCO
oscillation is stopped, it is possible to escape the deadlock by forcing the
charge pump output to low level and setting Vtune to VCC.
When a power-on reset is executed, normal operation mode is selected.
This is the IC test data.
Set TEST0 = 0.
TEST1 = 0
TEST2 = 0
* When a power-on reset is executed, all the test data is set to zero.
(12)
ULD
DT0, DT1
R0 to R3
(13)
UL1
DT0
E detection width
Detection pin output
0
Stop
Open
0
1
0
Direct output of E
1
0
±0.5
s
Extend E by 1 to 2 ms
11
±1
s
Extend E by 1 to 2 ms
Unlocked output
XS1
XS0
X’tal OSC
0
Prohibited
0
1
Prohibited
1
0
10.25 MHz
1
10.35 MHz
DZ1
DZ0
Dead zone mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
(14)
(15)
(16)
Extention
Crystal oscillator circuit
XS0, XS1
XB
Phase comparator control
data
DZ0, DZ1
Charge pump control data
DLC
IC test data
TEST0
TEST1
TEST2