參數(shù)資料
型號(hào): L9805
廠商: 意法半導(dǎo)體
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful
中文描述: 超級智能型電動(dòng)馬達(dá)驅(qū)動(dòng)器,帶有8位微控制器,CAN接口,16K的存儲(chǔ)器,256Bytes RAM內(nèi)存,128字節(jié)EEPROM,10位ADC,水分散粒劑,2定時(shí)器,2個(gè)PWM模塊,涪陵
文件頁數(shù): 80/103頁
文件大?。?/td> 853K
代理商: L9805
80/103
L9805
Note
The DIR signal is internally synchronized
with the PWM1 and PWM2 signals according to
the selected Driving Mode. After writing the DIR bit
in BCSR register, the direction changes in corre-
spondence with the first rising edge of PWM1. The
same procedure is used in the case of PWM2.
This allows the proper control of the direction
changes. When the PWM signal is 0% or 100%,
being no edges available, the DIR bit can’t be
latched and the direction does not change until a
PWM edge occurs.
P
1
1
0
0
0
1
0
1
0
1
BRAKE
Full Bridge
1
1
0
1
0
1
1
0
0
1
FORWARD
Full Bridge
1
1
1
0
0
1
0
1
0
1
BRAKE
Full Bridge
1
1
1
1
0
1
0
1
1
0
BACK
Full Bridge
P
1
1
0
0
1
0
0
1
1
0
BACK
Full Bridge
1
1
0
1
1
0
1
0
0
1
FORWARD
Full Bridge
1
1
1
0
1
0
1
0
0
1
FORWARD
Full Bridge
1
1
1
1
1
0
0
1
1
0
BACK
Full Bridge
P
1
1
0
1
1
pwm1 pwm1 pwm2 pwm2
PWM1 ->left
PWM2->right
Two Half
Bridges
1
1
1
1
1
pwm1 pwm1 pwm2 pwm2
PWM1 ->left
PWM2->right
Two Half
Bridges
Drive
EN PWM_EN DIR
PWM1 IN1 IN2
UL
DL
UR
DR
Operation Configuration
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