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參數(shù)資料
| 型號： | L9805 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Super Smart Power Motor Driver with 8-BIT MCU, CAN Interface, 16K EPROM, 256Bytes RAM, 128 Bytes EEPROM, 10 Bit ADC, WDG, 2 Timers, 2 PWM Modules, Ful |
| 中文描述： | 超級智能型電動馬達(dá)驅(qū)動器，帶有8位微控制器，CAN接口，16K的存儲器，256Bytes RAM內(nèi)存，128字節(jié)EEPROM，10位ADC，水分散粒劑，2定時器，2個PWM模塊，涪陵 |
| 文件頁數(shù)： | 28/103頁 |
| 文件大小： | 853K |
| 代理商： | L9805 |
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L9805
5 ON-CHIP PERIPHERALS
5.1 I/O PORTS
5.1.1 Introduction
The internal I/O ports allow the transfer of data
through digital inputs and outputs, the interrupt
generation coming from an I/O and for specific
pins, the input/output of alternate signals for the
on-chip peripherals (TIMERS...).
Each pin can be programmed independently as
digital input (with or without interrupt generation)
or digital output.
5.1.2 Functional Description
Each I/O pin may be programmed independently
as a digital input or a digital output, using the cor-
responding register bits.
Each port pin of the I/O Ports can be individually
configured under software control as either input
or output.
Each bit of a Data Direction Register (DDR) corre-
sponds to an I/O pin of the associated port. This
corresponding bit must be set to configure its as-
sociated pin as output and must be cleared to con-
figure its associated pin as input. The Data Direc-
tion Registers can be read and written.
5.1.2.1 Input Mode
When DDR=0, the corresponding I/O is configured
in Input mode.
In this case, the output buffer is switched off, the
state of the I/O is readable through the Data Reg-
ister address, but the I/O state comes directly from
the Schmitt-Trigger output and not from the Data
Register output.
5.1.2.2 Interrupt function
When an I/O is configured in Input with Interrupt
generation mode (DDR=0 and OR=1), a low level
or any transition on this I/O (according to the Mis-
cellaneous register configuration - see
Section
3.4
, “b3, b4 External Interrupt Option”) will gener-
ate an Interrupt request to the CPU.
Each pin can independently generate an Interrupt
request. When at least one of the interrupt inputs
is tied low, the port’s common interrupt will activate
a CPU interrupt input according to the external in-
terrupt option in the Miscellaneous Register.
5.1.2.3 Output Mode
When DDR=1, the corresponding I/O is configured
in Output mode. In this mode, the interrupt function
is disabled.
The output buffers can be individually configured
as Open Drain or Push-Pull by means of the Op-
tion Register.
The output buffer is activated according to the
Data Register’s content.
A read operation is directly performed from the
Data Register output.
5.1.2.4 Alternate function
A signal coming from a on-chip peripheral can be
output on the I/O.
In this case, the I/O is automatically configured in
output mode (without pull-up).
This must be controlled directly by the peripheral
with a signal coming from the peripheral which en-
ables the alternate signal to be output.
The I/O’s state is readable as in normal mode by
addressing the corresponding I/O Data Register.
A signal coming from an I/O can be input in a on-
chip peripheral.
Before using an I/O as Alternate Input, it must be
configured in Input without interrupt mode (DDR=0
and OR=0). So, both Alternate Input configuration
(with or without pull-up) and I/O input configuration
(with or without pull-up) are the same.
The signal to be input in the peripheral is taken af-
ter the Schmitt-trigger. The I/O’s state is readable
as in normal mode by addressing the correspond-
ing I/O Data Register.
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