參數(shù)資料
型號： L9230-DIE1
廠商： 意法半導體
英文描述： SPI CONTROLLED H-BRIDGE
中文描述： 可控的SPI H橋
文件頁數(shù)： 8/25頁
文件大?。?/td> 218K
代理商： L9230-DIE1
L9230
8/25
SPI INTERFACE
The timing of L9230 is defined as follows:
- The change at output (SO) is forced by the rising edge of the SCK signal.
- The input signal (SI) is taken over on the falling edge of the SCK signal.
- SS = active without any clocks at SCK is not allowed
- The data received during a writing access is taken over into the internal registers on the rising edge of the SS
signal, if exactly 16 SPI clocks have been counted during SS = active.
Figure 6.
ELECTRICAL CHARACTERISTCS
( continued)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Input SCK
(SPI clock input 4.5V < DMS < 5.5V)
V
SCKL
Low Level
1
V
V
SCKH
High Level
2
V
V
SCK
Hysteresis
0.1
0.4
V
C
SCK
Input Capacity
10
pF
SO
SI
MSB IN
Bit (n-4)...1
LSB IN
Bit (n-4)...1
1
4
5
6
SCK
SS
7
8
n = 16
9
10
3
2
Bit (n-3)
Bit 0; LSB
tristate
Bit (n-3)
Bit (n-2)
11
12
ELECTRICAL CHARACTERISTICS
(continued)
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