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參數(shù)資料
| 型號： | L9230-DIE1 |
| 廠商： | 意法半導體 |
| 英文描述： | SPI CONTROLLED H-BRIDGE |
| 中文描述： | 可控的SPI H橋 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大?。?/td> | 218K |
| 代理商： | L9230-DIE1 |
15/25
L9230
Characteristics of the SPI Interface
1)
When DMS is > 3,5V, the SPI is active, independent of the state of EN or DI and the voltage on V
S
.
During active reset conditions (DMS < 3,5V) the SPI is driven into its default state.
When reset becomes inactive, the state machine enters into a waitstate for the next instruction.
2)
If the slave select signal at SS is inactive (high), the state machine is forced to enter the
waitstate, i.e. the state machine waits for the following instruction.
3)
During active (low) state of the select signal SS the falling edge of the serial clock signal
SCK will be used to latch the input data at SI. Output data at SO are driven with the rising
edge of SCK. Further processing of the data according to the instruction ( i.e. modification
of internal registers) will be triggered by the rising edge of the SS signal. (-> See Note)
3 ) Chipaddress:
In order to establish the option of extended addressing the uppermost two bits of the
instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress.
To avoid a busconflict the output SO must stay high impedant during the addressing
phase of a frame (i.e. until the addressbits are recognised as valid chipaddress).
This tristate behavior should be realised in any case, regardless wether the extended
addressoption is used or not.
If the chipaddress does not match, the according access will be ignored and SO remains high
impedant for the complete frame regardless which frametype is applied.
5)
Check byte:
Simultaneously to the receipt of an SPI instruction L9230 transmitts a check byte via the
output SO to the controller. This byte indicates regular or irregular operation of the SPI.
It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access.
6)
On the read access the databits at the SPI input SI are rejected.
7)
Invalid instruction/access:
An instruction is invalid, if one of the following conditions is fulfilled:
- an unused instruction code is detected (see tables with SPI instructions).
- in case the previous transmission is not completed in terms of internal data processing.
( Violation of the minimum Access-Time. )
If an invalid instruction is detected, any modifications on registers of L9230 are not allowed.
In case an unused instruction code occured the databyte “ff
hex
” will be transmitted after
having sent the check byte.
In addition any access is invalid if the number of SPI clock pulses (falling edge) counted
during active SS differs from exactly 16 clock pulses (-> See Note).
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