參數(shù)資料
型號(hào)： L6740L
廠商： STMICROELECTRONICS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件頁數(shù)： 3/44頁
文件大?。?/td> 755K
代理商： L6740L
L6740L
Pins description and connection diagrams
31
NB
section
NB_VSEN
NB output voltage monitor.
It manages OVP and UVP protections and PWRGOOD. Connect to the
positive side of the NB load to perform remote sensing. See Section 9
for proper layout of this connection.
32
NB_DROOP
A current proportional to the total current read by the NB section is
sourced through this pin according to the current reading gain (RISEN).
Short to NB_FB to implement Droop Function or connect to SGND
through a resistor and filter with 1nF capacitor to implement NB LOAD
Indicator. If not used, short to SGND.
33
NB_FB
NB error amplifier inverting input.
Connect with a resistor RFB_NB to NB_VSEN and with an RF_NB - CF_NB
to NB_COMP. Offset current programmed by NB_OS is sunk through
this pin.
34
NB_COMP
Error amplifier output.
Connect with an RF_NB - CF_NB to NB_FB. The NB section or the device
cannot be disabled by grounding this pin.
35,
36
SVI
/
PVI
interf
ace
VID0, VID1
Voltage IDentification pins.
Internally pulled-low by 10
μA, they are used to program the output
voltage. VID1 is monitored on the EN pin rising-edge to define the
operative mode of the controller (SVI or PVI). When in SVI mode, VID0
is ignored. See Section 5 for details.
37
PWROK
System-wide Power Good input (SVI mode).
Internally pulled-low by 10
μA. When low, the device will decode the two
SVI bits (SVC, SVD) to determine the Pre-PWROK Metal VID (default
condition when pin is floating).
When high, the device will actively run the SVI protocol.
Pre-PWROK Metal VID are latched after EN is asserted and re-used in
case of PWROK de-assertion. Latch is reset by VCC or EN cycle.
38
EN
VR Enable. Internally pulled-up to 3.3 V by 10
μA.
Pull-low to disable the device. When set free, the device immediately
checks for the VID1 status to determine the SVI / PVI protocol to be
adopted and configures itself accordingly. See Section 5 for details.
39
SVI
/PVI
interf
ace
SVC / VID3
Voltage IDentification pin - SVI clock pin.
Internally pulled-low by 10
μA, it is used to program the output voltage.
When in SVI-mode, it is considered as Serial-VID-data (input / open
drain output). See Section 5 for details.
40
SVD / VID2
Voltage IDentification pins - SVI data pin.
Internally pulled-low by 10
μA, it is used to program the output voltage.
When in SVI-mode, it is considered as Serial-VID-data (input / open
drain output). See Section 5 for details.
41
PWRGOOD
VCORE and NB Power Good.
It is an open-drain output set free after SS as long as both the voltage
planes are within specifications. Pull-up to 3.3V (typ) or lower, if not
used it can be left floating.
When in PVI mode, it monitors the CORE section only.
Table 2.
Pin description (continued)
Pin#
Name
Function
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參數(shù)描述
L6740LTR 功能描述:DC/DC 開關(guān)控制器 Hybrid controller RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
L6741 功能描述:功率驅(qū)動(dòng)器IC SnglPphase Dual MOSFET Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
L6741TR 功能描述:功率驅(qū)動(dòng)器IC SnglPphase Dual MOSFET Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
L6743 功能描述:功率驅(qū)動(dòng)器IC SnglPphase Dual MOSFET Driver RoHS:否 制造商:Micrel 產(chǎn)品:MOSFET Gate Drivers 類型:Low Cost High or Low Side MOSFET Driver 上升時(shí)間: 下降時(shí)間: 電源電壓-最大:30 V 電源電壓-最小:2.75 V 電源電流: 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
L6743_08 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:High current MOSFET driver
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