參數(shù)資料
型號: L6740L
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, HTQFP-48
文件頁數(shù): 11/44頁
文件大?。?/td> 755K
代理商: L6740L
L6740L
Hybrid CPU support and CPU_TYPE detection
transition for the addressed section(s) or, more in general, react to the sent command
accordingly. Refer to Figure 7, Table 8 and Table 9 for details about the Set VID command.
L6740L is able to manage individual power OFF for both the sections. The CPU may issue a
serial VID command to power OFF or power ON one section while the other one remains
powered. In this case, the PWRGOOD signal remains asserted.
Figure 7.
SVI communications - send byte
Table 8.
SVI send byte - Address and data phase description
bits
Description
Address phase
6:4
Always 110b.
3
Not applicable, ignored.
2
Not applicable, ignored.
1
CORE section(1).
If set then the following data byte contains the VID code for CORE section.
1.
Assertion in both bit 1 and 0 will address the VID code to both CORE and NB simultaneously.
0
NB section(1).
If set then the following data byte contains the VID code for NB section.
Data phase
7
PSI_L Flag (active low).When asserted, the VR is allowed to enter power-saving
mode. See Section 5.4.3.
6:0
VID code. See Table 9.
SVC
SVD
START
110b
ACK
Slave Addressing
(7 Clocks)
654
0
WRITE
(1Ck)
ACK
(1Ck)
76
0
3
Data Phase
(8 Clocks)
ACK
(1Ck)
STOP
START
SLAVE ADDRESSING + W
ACK
DATA PHASE
ACK
STOP
BUS DRIVEN BY L6740L
BUS DRIVEN BY MASTER (CPU)
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