參數(shù)資料
型號: L6728TR
廠商: 意法半導(dǎo)體
英文描述: Single phase PWM controller with PowerGOOD
中文描述: 單相PWM控制器與電源良好
文件頁數(shù): 15/32頁
文件大?。?/td> 942K
代理商: L6728TR
L6728
Application details
15/32
10
Application details
10.1
Compensation network
The control loop showed in
Figure 5
is a voltage mode control loop. The output voltage is
regulated to the internal reference (when present, offset resistor between FB node and GND
can be neglected in control loop calculation).
Error Amplifier output is compared to oscillator saw-tooth waveform to provide PWM signal
to the driver section. PWM signal is then transferred to the switching node with V
IN
amplitude. This waveform is filtered by the output filter.
The converter transfer function is the small signal transfer function between the output of the
EA and V
OUT
. This function has a double pole at frequency F
LC
depending on the L-C
OUT
resonance and a zero at F
ESR
depending on the output capacitor ESR. The DC Gain of the
modulator is simply the input voltage V
IN
divided by the peak-to-peak oscillator voltage
V
OSC
.
Figure 5.
PWM control loop
The compensation network closes the loop joining V
OUT
and EA output with transfer
function ideally equal to -Z
F
/
Z
FB
.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
0dB
) can be fixed choosing the right R
F
/R
FB
ratio, however, for
stability, it should not exceed F
SW
/2
π
. To achieve a good phase margin, the control loop gain
has to cross 0dB axis with -20dB/decade slope.
As an example,
Figure 6
shows an asymptotic bode plot of a type III compensation.
L
R
C
OUT
ESR
R
F
C
F
C
P
R
FB
C
S
OSC
V
IN
V
OSC
+
+
_
_
V
OUT
V
REF
Z
F
Z
FB
PWM
COMPARATOR
ERROR
AMPLIFIER
R
S
相關(guān)PDF資料
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