參數(shù)資料
型號(hào): L6717
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: DUAL SWITCHING CONTROLLER, 575 kHz SWITCHING FREQ-MAX, QCC48
封裝: 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFPN-48
文件頁(yè)數(shù): 37/56頁(yè)
文件大?。?/td> 1081K
代理商: L6717
Output voltage monitoring and protections
L6717
42/56
Doc ID 17326 Rev 1
Figure 13.
Analog OVP threshold
When the voltage sensed by VSEN and/or NB_VSEN overcomes the OV threshold, the con-
troller:
Permanently sets the PWM of the involved section to zero keeping ENDRV of that
section high in order to keep all the low-side MOSFETs on to protect the load of
the section in OV condition.
Permanently sets the PWM of the non-involved section to HiZ while keeping
ENDRV of the non-involved section low in order to realize an HiZ condition of the
non-involved section.
Drives the OSC/ FLT pin high.
Power supply or EN pin cycling is required to restart operations.
Filter OVP pin with 1nF(typ) to SGND.
8.2
Feedback disconnection
L6717 provides both CORE and NB sections with FB disconnection protection. This feature
acts in order to stop the device from regulating dangerous voltages in case the remote
sense connections are left floating. The protection is available for both the sections and
operates for both the positive and negative sense.
According to Figure 14, the protection works as follow:
CORE section:
Positive sense is performed monitoring the CORE output voltage through both VSEN
and CS1N. As soon as CS1N is more than 600 mV higher than VSEN, the device
latches in HiZ. FLT pin is driven high. A 30
μA pull-down current on the VSEN forces
the device to detect this fault condition.
Negative sense is performed monitoring the internal OpAmp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
soon as the difference between the output and the input of this OpAmp is higher than
500 mV, the device latches in HiZ. FLT pin is driven high.
NB section (SVI only)
Positive sense is performed monitoring the NB output voltage through both NB_VSEN
and NB_CSN. As soon as NB_CSN is more than 600 mV higher than NB_VSEN, the
device latches in HiZ. FLT pin is driven high. A 30
μA pull-down current on the
NB_VSEN forces the device to detect this fault condition.
Negative sense is performed monitoring the internal OpAmp used to recover the GND
losses by comparing its output and the internal reference generated by the DAC. As
SDA/OVP
ROVPH
Analog OVP Setting (I2C Disabled)
3V3
ROVPL
COVP
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