參數(shù)資料
型號(hào)： L6717
廠商： STMICROELECTRONICS
元件分類(lèi)： 穩(wěn)壓器
英文描述： DUAL SWITCHING CONTROLLER, 575 kHz SWITCHING FREQ-MAX, QCC48
封裝： 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFQFPN-48
文件頁(yè)數(shù)： 31/56頁(yè)
文件大小： 1081K
代理商： L6717
L6717
Output voltage positioning
Doc ID 17326 Rev 1
37/56
7.4
CORE section - analog offset (Optional - I2CDIS = 3.3 V)
When power manager I2C is disabled (I2CDIS = 3.3 V), L6717 still provide the way to add
positive/negative offset to the CORE section. In this particular conditions, the pin SCL/OS
becomes a virtual ground and allows programming a positive/negative offset (VOS) for the
CORE section output voltage by connecting a resistor ROS to SGND/VCC. The pin is inter-
nally fixed at 1.240 V (2.0 V in case of negative offset, ROS tied to VCC) so a current is pro-
grammed by connecting the resistor ROS between the pin and SGND/VCC: this current is
mirrored and then properly sunk/sourced from the FB pin as shown in Figure 9. Output volt-
age is then programmed as follow:
Offset resistor can be designed by considering the following relationship (RFB is be fixed by
the droop effect):
(positive offset)
(negative offset)
Caution:
Offset implementation is optional, in case it is not desired, simply short the pin to GND.
Note:
In the above formulas, RFB has to be considered being the total resistance connected
between FB pin and the regulated voltage. kDRP has to be considered having its default
value since power manager I2C is disabled.
7.5
NB section - current reading
NB section performs the same differential current reading across DCR as the CORE Sec-
tion. According to Section 7.2, the current that flows from the NB_CSN pin is then given by
the following equation (See Figure 10):
RG_NB resistor is typically designed according to the OC threshold. See Section 8.4 for
details.
7.6
NB section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-
dence of the output voltage on the load current, a static error, proportional to the output cur-
rent, causes the output voltage to vary according to the sensed current.
Figure 10 shows the current sense circuit used to implement the load-line. The current flow-
ing across the inductor DCR is read through RG_NB. RG_NB programs a trans-conductance
gain and generates a current IDROOP_NB proportional to the current delivered by the NB
Section that is then sourced from the NB_FB pin with proper gain defined by the DRP_ADJ
V
CORE
VID
R
FB
k
DRP
I
DROOP
I
OS
–
()
–
=
R
OS
1.240V
V
OS
------------------- R
FB
=
R
OS
VCC
2.0V
–
V
OS
-------------------------------- R
FB
=
I
NB_CSN
DCR(NB)
R
G_NB
------------------------- I
NB
I
DROOP_NB
==
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L6718TR 功能描述:其他電源管理 Multiphase Dual PWM VR12 25MHz LTB RoHS:否 制造商:Texas Instruments 輸出電壓范圍: 輸出電流:4 mA 輸入電壓范圍:3 V to 3.6 V 輸入電流: 功率耗散: 工作溫度范圍:- 40 C to + 110 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-48 封裝:Reel
L6720 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:
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