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參數資料
| 型號： | L6245 |
| 廠商： | 意法半導體 |
| 英文描述： | 5V HARD DISK DRIVE POWER COMBO |
| 中文描述： | 5V的硬盤驅動器電源組合 |
| 文件頁數： | 12/15頁 |
| 文件大?。?/td> | 191K |
| 代理商： | L6245 |
cycle. On a write operation, following write going
low and whatever setup time required to latch
data, data acknwledgeis driven low. This notifies
the processorthat the cycle can end. This proces-
sor responds by raising write, indicating the end
of the cycle. Data acknowledge must go to high
impedance within 20nsec to clear the bus for the
next cycle.
This handshaking design allows a peripheral to
control the lengthof the bus cycle. The peripheral
can take as much time as it needs to drive data
onto the bus, then drive DTACK low. Likewise,
the peripheral can wait as long as it needs to set
up data and latch it (or set up data if WR is used
to latch), then drive DTACK low. However, per-
formance is an issue, so even though this control
has been given to the peripheral, it must not be
abused. All delays are minimized to assure opti-
mum system speed, infact the bus can be driven
synchronously(E.G. has regarding DTACK) when
procesorclocks below 12MHz are used.
Figure1:
SystemBus Timing (see Table 8)
Table 8:
System Bus Timing
Symbol
TAS
TCS
TASW
TASRD
TRDDV
TRDDH
TRDCS
TDVDT
TDTRD
TRDDT
TASWR
TDVWR
TWRDTL
TDTWR
TWRCS
TWRDT
TWRDH
Description
Address Setup Time (non MUX bus; (MUX bus)
System Select to Address Strobe
Address StrobeWidth
Address Strobeto RD
RD to Data Driven
Read Data Hold
RD High to CS High
Data Valid toDTACK
DTACK to RD High
RD High to DTACH High
Address Strobeto WR
Write Data Valid to WR
WR to DTACK
DTACK to WR High
WR High to CS High
WR High to DTACK High
Write Data Hold
L6245
12/15
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| L6254 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL “COMBO” |
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