參數(shù)資料
型號(hào): L6237
廠商: 意法半導(dǎo)體
英文描述: 5V Spindle Motor Driver(5V主軸電機(jī)驅(qū)動(dòng)器)
中文描述: 5V的主軸電機(jī)驅(qū)動(dòng)器(5V的主軸電機(jī)驅(qū)動(dòng)器)
文件頁(yè)數(shù): 5/11頁(yè)
文件大?。?/td> 145K
代理商: L6237
SPINDLEDRIVE FUNCTIONAL DESCRIPTION
The commutation is accomplished via three logic
inputs (CLOCK, RESET, MUX_SGL). A positive
transition at the clock input will increment the in-
ternal sequencer producing commutation to the
next phase (refer to logic truth table for explana-
tion of sequenceroperations).
The L6237 performs internal sensing of the Back
Electromotive Force (BEMF), giving a CMOS
compatible logic output signal that is high or low if
the current BEMF voltage is respectivelyabove or
below the central tap voltage. For application in
which the center tap is not connectable to the
relative input pin, three resistors are internally
available from outputs in a ”Y” configuration to
simulate the presence of the center tap. The
BEMF comparator input is internally switched to
the output phase that is in tristate condition, while
the output is selectable via the MUX_SGL input.
When MUX mode is selected the BEMF output
will track the current floating phase, as deter-
mined by the sequencer state. When SGL mode
is active, only the C outputBEMFis provided.
The L6237 performs an adaptive digital mask to
block unwanted zero crossing generated during
phases commutation. This mask is activated
when a positiveCLOCK transitionincrements the
sequencer,and remainsactive for a period that is
one fourth of the period between two zero cross-
ing. Considering that a full increment of the se-
quencer(one ”electrical” revolution) gives 6 differ-
ent output states, the period between two
commutation can be considered of 60 electrical
degrees, so that the masking time is 15 electrical
degrees. An input clock signal FREF is requireed
asa timebase for the internal mask counters.
The BRK and BRK_DLY inputs offer flexibility to
the system designer in the implementation of the
brakingfunction. The BRK input, when pulled low,
turns off all upper and lower DMOS drivers. This
Figure1:
SequencerTiming Diagram.
SEQUENCER STATES
OUTA
STATE1
STATE2
STATE3
STATE4
STATE5
STATE6
LOGIC BRK
(SEQ->STATE1)
SEQUENCER TRUTH TABLE
MUX_SGL
0
Single BEMF
1
MUX BEMF
0
Initialize Sequencer
1
Tri-State, MUX BEMF
0
Logic Brake, Initialize Seq.
OUTB
I-
0
I+
I+
0
I-
I-
OUTC
0
I-
I-
0
I+
I+
I-
CLK
X
X
0
X
1
RESET
0
0
1
1
1
OPERATING MODE
I+
I+
0
I-
I-
0
I-
Drivers
Enabled
X = DON’T CARE
Indicates not level sensitive, increments sequenceron positive edge
I+: Upper On, I-:Lower On, 0:Tri-State
L6237
5/11
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