參數(shù)資料
型號: L6000
廠商: 意法半導(dǎo)體
英文描述: SINGLE CHIP READ & WRITE CHANNEL
中文描述: 單芯片讀
文件頁數(shù): 16/24頁
文件大?。?/td> 279K
代理商: L6000
asserted, then the SERIAL CLOCK+ is driven
with the positive edge latching the state of SE-
RIAL DATA. The actual data is latched into each
register in the L6000 when SERIAL ENABLE is
disasserted, so this signal MUST be driven low
after EACH register write; failure to deassert SE-
RIAL ENABLE before a 17th SERIAL CLOCK+
will erase ( invalidate ) the previous 16 clock cy-
cles. This also precludes SERIAL CLOCK+ from
being a free running clock in the system. The
The internal register map for the serial port is shownbelow:
Address Bits
Blk Diagr.
Address
Symbol
Function
LSB
0
0
1
1
0
0
0
0
0
0
1
1
0
The bit map of each register(except CA, CB & PD) is as follows:
MSB
5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
2
0
0
0
0
0
0
1
1
1
1
1
1
3
0
0
1
1
0
1
0
1
0
0
1
1
4
0
0
0
0
1
1
0
0
0
0
0
0
6
0
0
0
0
0
0
0
0
0
0
0
0
R02
R03
R0B
R0A
R12
R1A
R06
R0E
R04
R05
R0D
R0C
PD
FCutoff
FBoost
DVTH
SVTH
CA
PSNN
PSMM
VCO CENT
WIN SHIFT
WRT PREC
CB
Power Down Mode Control
DACF-Filter cutoff Frequency Control
DACS-Filter Boost Control
Pulse Detector Voltage Threshold Control (Data Read Mode)
Pulse Detector Voltage Threshold Control (Servo Read Mode)
Control A (PulseDetector, Filter, frequency synthesizer Control)
Counter Value (frequency synthesizer)
Counter Value (frequency synthesizer)
VCO CenterFrequency
Window Shift Magnitude,Direction
Write Precomp magnitude
Control B (Data Separator, Endec Control)
FCutoff register
FBoost register
DVTH register
SVTH register
PSN register
PSM register
VCO CENT register
WIN SHIFT register
WRT PREC register
where:
X
X
DEDC
SEDC
X
M7
FSC
TDAC1
X
X = Unused bit or don’t care bit
DEDC = Enable dual comparator qualifier in Data read mode.
SEDC = Enable dual comparator qualifier in Servo read mode.
FSC = The frequency synthesizer back comparator state
TDAC1 = DAC Testing control bit #1
TDAC0 = DAC Testing control bit #0
FC6
FB6
VD6
VS6
N6
M6
DR6
TDAC0
X
FC5
FB5
VD5
VS5
N5
M5
DR5
WSE
X
FC4
FB4
VD4
VS4
N4
M4
DR4
WSD
X
FC3
FB3
VD3
VS3
N3
M3
DR3
WS3
WP3
FC2
FB2
VD2
VS2
N2
M2
DR2
WS2
WP2
FC1
FB1
VD1
VS1
N1
M1
DR1
WS1
WP1
FC0
FB0
VD0
VS0
N0
M0
DR0
WS0
WP0
Control register CA:
Function
Enable Phase Detector (frequency
synthesizer)
Pump Up (FLTR1 sources current,
FLTR1 sinks current) Test mode
Pump Down (FLTR1 sinkscurrent,
FLTR1 sources current) Test Mode
Enable frequency synthesizer Circuit
Function
Bypass frequency synthesizer Circuit
Function
TEST Enable Pulse Detector Test
Points, COUT and DOUT
Force AGC Charge Pump into Fast
Decay Mode
Unused
Control register CB:
Function
Direct Write (Bypass Endec)
Bit
0
Symbol
EPDT
Bit
0
Symbol
DW
1
UT
1
GS
Enable Phase Detector Gain
Switching
2
DT
2
READDATAI/O Pin Input Control
3
ET
3
EPDD
Enable Phase Detector (Data
Separator)
Pump Up (FLTR2 sources current,
FLTR2 sinks current) Test mode
Pump Down (FLTR sinks current,
FLTR2 sources current) Test mode
Enable Data Separator Test Point
Outputs
Select Soft or Hard Sector Operation
4
BYPT
4
UD
5
PD
5
DD
6
FDCT
6
ED
7
7
SOFT
L6000
16/24
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