參數(shù)資料
型號(hào): L6000
廠商: 意法半導(dǎo)體
英文描述: SINGLE CHIP READ & WRITE CHANNEL
中文描述: 單芯片讀
文件頁(yè)數(shù): 12/24頁(yè)
文件大?。?/td> 279K
代理商: L6000
PROGRAMMABLE FILTER CHARACTERISTICS
(continued)
Symbol
EOUT
Parameter
Test Condition
Min.
Typ.
2
Max.
7
Unit
mVrms
Output Noise Voltage
Differentiated Output
Output Noise Voltage Normal
Output
Output Noise Voltage
Differentiated Output
Output Noise Voltage Normal
Output
Filter Output SinkCurrent
Filter Output Source Current
Filter Output resistance Single
Ended
BW = 100MHz, Rs = 50
FC = 18MHz, DACS = 0
1.2
5
mVrms
BW = 100MHz, Rs = 50
FC = 18MHz, DACS = 127
4.6
7
mVrms
2
5
mVrms
IO-
IO+
RO
0.5
2.0
mA
mA
200
Note: FBDAC is value of boost DAC (i.e., no boost)
Filter Control Characteristics (RX = 12K
)
VRX
Reference Current Set Output
Voltage
FREQUENCY SYNTHESIZER CHARACTERISTICS (RR = 39K
)
T
amb
= 27
°
C
(**)
1.5
V
FIN
FOUT
JFO
Input Frequency
Output Frequency
FOUT jitter
M DivideNumber
N Divide Number
VCO CenterFrequency Period
8
80
25
20
96
MHz
MHz
ps(pk)
ns
TO = 1/FO; Fout = 30MHz
±
400
255
127
1.1TO
TVCO
TO = (9.65 + 0.843
x
DR)
-1
FLTR1-FLTR1= 0
(***)
–1.5
FLTR1-FLTR1
+1.5,
Fout = 54.0MHz
(***)
ω
= 2
π
/TVCO
–1.5
FLTR1-FLTR1
+1.5
KD = 0.7 + 0.43
x
DR
(***)
0.9TO
VCO Frequency Dynamic
Range
VCO Control Gain
25
±
45
%
KVCO
0.14
ω
o
0.26
ω
o
rad/(V-s)
KD
Phase Detector Gain
KVCO x KD Product Accuracy
Reference Clock Characteristics:
Reference Clock Low Time
Reference Clock High Time
DATA SEPARATOR DYNAMIC CHARACTERISTICS AND TIMING
(Unless otherwise specified, rec-
ommendedoperating conditionsapply.)
0.83KD
– 28
1.17KD
+ 28
μ
A/rad
%
20
20
ns
ns
Real Mode
TRRC
TFRC
Read Clock Rise Time
Read Clock Fall time
RRC Duty Cycle
NRZ(out) Set Up and Hold Time
0.8V to 2.0V,CL
15pF
2.0V to 0.8V,CL
15pF
DR = 32Mbit/s
DR
20Mbit/s
(**)
DR > 20Mbit/s
(**)
(**)
43
15.5
13
8
5
57
±
15
ns
ns
%
ns
ns
ns
TNS, TNH
TPNRZ
NRZ (out) Propagation Delay
(**)
Bench test only.
(***)
Preliminary data.
L6000
12/24
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