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參數(shù)資料
| 型號： | L4C381 |
| 廠商： | Logic Devices Incorporated |
| 英文描述： | High Speed,Cascadable 16-bit Arithmetic and Logic Unit(高速層疊16位算術(shù)和邏輯單元) |
| 中文描述： | 高速，可級聯(lián)16位算術(shù)邏輯單元（高速層疊16位算術(shù)和邏輯單元） |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | L4C381 |
DEVICES INCORPORATED
L4C381
16-bit Cascadable ALU
Arithmetic Logic Units
08/16/2000–LDS.381-P
9
C
ASCADING
THE
L4C381
(of the C
0
setup time, if the F register
is used). The sum gives the overall
input-to-output delay (or setup time)
for the 32-bit configuration. This
method gives a conservative result,
since the C
16
output is very lightly
loaded. Formulas for calculation of
all critical delays for a 32-bit system
are shown in Figures 4A through 4D.
Cascading to greater than 32 bits can
be accomplished in two ways: The
simplest (but slowest) method is to
simply connect the C
16
output of each
slice to the C
0
input of the next more
significant slice. Propagation delays
are calculated as for the 32-bit case,
except that the C
0
to C
16
delays for all
intermediate slices must be added to
the overall delay for each path. A
faster method is to use an external
carry-lookahead generator. The P and
G outputs of each slice are connected
as inputs to the CLA generator, which
in turn produces the C
0
inputs for
each slice except the least significant.
The C
16
outputs are not used in this
case, except for the most significant
one, which is the carry out of the
overall system. The carry in to the
system is connected to the C
0
input of
the least significant slice, and also to
the carry lookahead generator.
Propagation delays for this configura-
tion are the sum of the time to P, G,
for the least significant slice, the
propagation delay of the carry look-
ahead generator, and the C
0
to output
time of the most significant slice.
Cascading the L4C381 to 32 bits is
accomplished simply by connecting
the C
16
output of the least significant
slice to the C
0
input of the most sig-
nificant slice. The S
2
-S
0
, OSA, OSB,
ENA, ENB, and ENF lines are
common to both devices. The Zero
output flags should be logically
ANDed to produce the Zero flag for
the 32-bit result. The OVF and C
16
outputs of the most significant slice
are valid for the 32-bit result.
Propagation delay calculations for this
configuration require two steps: First
determine the propagation delay from
the input of interest to the C
16
output
of the lower slice. Add this number
to the delay from the C
0
input of the
upper slice to the output of interest
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| L4C381EC26 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fixed Point ALU |
| L4C381EC40 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Fixed Point ALU |
| L4C381EC-40 | 制造商:LOGIC 功能描述: |
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