參數(shù)資料
型號(hào)： L4C381
廠商： Logic Devices Incorporated
英文描述： High Speed,Cascadable 16-bit Arithmetic and Logic Unit(高速層疊16位算術(shù)和邏輯單元)
中文描述： 高速，可級(jí)聯(lián)16位算術(shù)邏輯單元（高速層疊16位算術(shù)和邏輯單元）
文件頁(yè)數(shù)： 11/12頁(yè)
文件大小： 85K
代理商： L4C381
DEVICES INCORPORATED
L4C381
16-bit Cascadable ALU
Arithmetic Logic Units
08/16/2000–LDS.381-P
11
F
IGURE
4C.
FTAB = 1, FTF = 0
From
Clock
A, B
C
0
S
2
-S
0
, OSA, OSB
A, B
C
0
S
2
-S
0
, OSA, OSB
ENA, ENB, ENF
Minimum cycle time
(F register accumulate loop)
To
F
Other
Other
Other
Setup time
Setup time
Setup time
Setup time
Calculated Specification Limit
Same as 16-bit case
(A, B
C
16
) + (C
0
Out)
(C
0
C
16
) + (C
0
Out)
(S
2
-S
0
, OSA, OSB
C
16
) + (C
0
Out)
(A, B
C
16
) + (C
0
Setup time)
(C
0
C
16
) + (C
0
Setup time)
(S
2
-S
0
, OSA, OSB
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
C
16
) + (C
0
Setup time)
=
=
=
=
=
=
=
=
=
F
IGURE
4D.
FTAB = 1, FTF = 1
From
A, B
A, B
C
0
C
0
S
2
-S
0
, OSA, OSB
S
2
-S
0
, OSA, OSB
A, B
C
0
S
2
-S
0
, OSA, OSB
ENA, ENB, ENF
Minimum cycle time
(F register accumulate loop)
To
F
Other
F
Other
F
Other
Setup time
Setup time
Setup time
Setup time
Calculated Specification Limit
(A, B
C
16
) + (C
0
F)
(A, B
C
16
) + (C
0
Out)
(C
0
C
16
) + (C
0
F)
(C
0
C
16
) + (C
0
Out)
(S
2
-S
0
, OSA, OSB
C
16
) + (C
0
F)
(S
2
-S
0
, OSA, OSB
C
16
) + (C
0
Out)
(A, B
C
16
) + (C
0
Setup time)
(C
0
C
16
) + (C
0
Setup time)
(S
2
-S
0
, OSA, OSB
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
C
16
) + (C
0
Setup time)
=
=
=
=
=
=
=
=
=
=
=
16
D
Q
A
31
-A
16
A
F
B
C
0
16
D
Q
A
F
B
C
0
CLOCK
CLOCK
OSA, OSB
MOST
SIGNIFICANT
SLICE
LEAST
SIGNIFICANT
SLICE
S
2
–S
0
C
0,
C
16
B
31
-B
16
F
31
-F
16
A
15
-A
0
B
15
-B
0
F
15
-F
0
16
A
31
-A
16
A
F
B
C
0
16
A
F
B
C
0
OSA, OSB
MOST
SIGNIFICANT
SLICE
LEAST
SIGNIFICANT
SLICE
S
2
–S
0
C
0,
C
16
B
31
-B
16
F
31
-F
16
A
15
-A
0
B
15
-B
0
F
15
-F
0
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