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參數(shù)資料
| 型號： | KT8554B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | Codec |
| 英文描述： | 1 Chip Codecs(編解碼器) |
| 中文描述： | 1芯片解碼器（編解碼器） |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 136K |
| 代理商： | KT8554B |
KT8554B/7B 1 CHIP CODECS
TIMING CHARACTERISTICS
(Continued)
Note 1 : For short frame sync timing, FS
X
and FS
R
must go high while their respective bit clocks are high.
TIMING DIAGRAM
Fig. 2. Short Frame Sync Timing
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Hold Time from BCLK
X/R
Low
to FS
X/R
Low
Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FS
X
or FS
R
)
Minimum Width of the Frame
Sync Pulse (Low Level)
Short frame sync pulse (1 or 2 bit
clock periods long) (Note 1)
t
H (3rd )
Long frame sync pulse (from 3 to
8 bit clock periods long)
100
ns
t
H (BLFL)
t
WFL
64K bit/s operating mode
100
160
ns
ns
t
D (LDD)
t
D (TS X L)
t
H (BLDR)
t
H (BLDR)
t
SU (DR BL)
t
H (BLFL)
t
H (HFS)
t
SU (FBCL)
t
D (LDD)
t
D (HDV)
t
SU (BHMF)
t
H (HFS)
t
SU (FBLS)
t
H (BLFL)
t
W (MCKH)
t
CK
t
W (MCKL)
t
F (MCK)
t
R (MCK)
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