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參數(shù)資料
| 型號： | KT8554B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | Codec |
| 英文描述： | 1 Chip Codecs(編解碼器) |
| 中文描述： | 1芯片解碼器（編解碼器） |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 136K |
| 代理商： | KT8554B |
KT8554B/7B 1 CHIP CODECS
TIMING CHARACTERISTICS
(Unless otherwise noted
,
V
CC
= 5.0
±
5%, V
BB
= -5.0V
±
5%, GNDA = 0V, Ta = 0
o
C to 70
o
C; typical characteristics
specified at V
CC
= 5.0V, V
BB
= -5.0V, Ta = 25
o
C; all signals referenced to GNDA.)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Frequency of Master Clocks
f
MCK
Depends on the device used and the
BCLK
R
/CLKSEL Pin.
MCLK
X
and MCLK
R
1.536
1.544
2.048
MHz
MHz
MHz
Rise Time of Bit Clock
t
R (BCK)
t
PB
= 488ns
50
ns
Fall Time of Bit Clock
t
F (BCK)
t
PB
= 488ns
50
ns
Holding Time from Bit Clock
Low to Frame Sync
Holding Time from Bit Clock
High to Frame Sync
Set-Up Time from Frame Sync
to Bit Clock Low
Delay Time from BCLK
X
High
to Data Valid
0
ns
0
ns
80
ns
0
180
ns
Delay Time to TS
X
Low
t
D
(TSXL)
Load = 150pF plus 2 LSTTL loads
140
ns
Delay Time from BCLK
X
Low to
Data Output Disabled
Delay Time to Valid Data from
FS
X
or BCLK
X
, Whichever
Comes Later
Set-Up Time from D
R
Valid to
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low
to D
R
Invalid
Set-Up Time from FS
X/R
to
BCLK
X/R
Low
50
165
ns
t
D (VD)
C
L
= 0pF to 150pF
20
165
ns
50
ns
50
ns
Short frame sync pulse (1 or 2 bit
clock periods long) (Note1)
50
ns
Width of Master Clock High
t
W (MCKH)
MCLK
X
and MCLK
R
160
ns
Width of Master Clock Low
t
W (MCKL)
MCLK
X
and MCLK
R
160
ns
Rise Time of Master Clock
t
R (MCK)
MCLK
X
and MCLK
R
50
ns
Fall Time of Master Clock
t
F( MCK)
MCLK
X
and MCLK
R
50
ns
Set-Up Time from BCLK
X
High
(and FS
X
In Long Frame Sync
Mode) to MCLK
X
Falling Edge
t
SU (BHMF)
Period of Bit Clock
t
CK
485
488
15,72
5
ns
Width of Bit Clock High
t
W (BCKH)
V
IH
= 2.2V
160
ns
Width of Bit Clock Low
t
W (BCKL)
V
IL
= 0.6V
160
ns
t
H (LFS)
t
H (HFS)
t
SU (FBCL)
t
D (HDV)
t
D (LDD)
t
SU (DR BL)
t
H (BL DR)
t
SU (FBLS)
Long frame only
Short frame only
Long frame only
Load = 150pF plus 2 LSTTL loads
First bit clock after the leading
edge of FS
X
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