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參數(shù)資料
| 型號： | KSZ9021RNI |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 37/58頁 |
| 文件大小： | 0K |
| 描述： | IC TXRX 10/100/1000 SGL 48QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 8/8 |
| 規(guī)程： | 千兆位以太網(wǎng) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
| 配用： | 576-3874-ND - BOARD EVALUATION FOR KSZ9021RN |
| 其它名稱： | 576-3978 KSZ9021RNI-ND |
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MCP444X/446X
DS22265A-page 42
2010 Microchip Technology Inc.
4.2
Memory Map
The device memory has 16 locations that are 9-bit wide
(16x9 bits). This memory space contains both volatile
and nonvolatile locations (see Table 4-1).
TABLE 4-1:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Function
Memory
Type
Allowed Commands
Disallowed Commands (2)
Factory
Initialization
00h
Volatile Wiper 0
RAM
Read, Write,
Increment, Decrement
—
01h
Volatile Wiper 1
RAM
Read, Write,
Increment, Decrement
—
02h
Nonvolatile Wiper 0
EEPROM
Read, Write (1)
Increment, Decrement
8-bit
80h
7-bit
40h
03h
Nonvolatile Wiper 1
EEPROM
Read, Write (1)
Increment, Decrement
8-bit
80h
7-bit
40h
04h
Volatile
TCON0 Register
RAM
Read, Write
Increment, Decrement
—
05h
Status Register
RAM
Read
Write, Increment, Decrement
—
06h
Volatile Wiper 2
RAM
Read, Write,
Increment, Decrement
—
07h
Volatile Wiper 3
RAM
Read, Write,
Increment, Decrement
—
08h
Nonvolatile Wiper 2
EEPROM
Read, Write (1)
Increment, Decrement
8-bit
80h
7-bit
40h
09h
Nonvolatile Wiper 3
EEPROM
Read, Write (1)
Increment, Decrement
8-bit
80h
7-bit
40h
0Ah
Volatile
TCON1 Register
RAM
Read, Write
Increment, Decrement
—
0Bh
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
0Ch
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
0Dh
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
0Eh
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
0Fh
Data EEPROM
EEPROM
Read, Write (1)
Increment, Decrement
000h
Note 1:
When an EEPROM write is active, these are invalid commands and will generate an error condition. The
user should use a read of the Status register to determine when the write cycle has completed. To exit the
error condition, the user must take the HVC pin to the VIH level and then back to the active state (VIL or
VIHH).
2:
This command on this address will generate an error condition. To exit the error condition, the user must
take the HVC pin to the VIH level and then back to the active state (VIL or VIHH).
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